Thalia takes machine learning in EDA tool down to 22nm FDSOI
The Technology Analyzer and Circuit Porting tools from Thalia add machine learning to accelerate analysis and porting of analog IP between process nodes to improve design productivity.
The enhancements to the tools in the Amalia IP reuse and development platform also support a broader set of process technologies down to 22nm FDSOI low power processes. This opens up a wider range of applications, including IoT devices, MCUs, 5G infrastructure, radar and RF, says he company.
In addition, Thalia has enhanced its Technology Analyzer software to extract the noise, DC, AC characteristics over corners and Monte Carlo analysis.
Thalia now uses machine learning across the whole platform to analyze waveforms and propose candidate solutions for designers, based on differential analyses. Simplifying porting of IP to a new process node is a critical element in moving parts away from foundry processes that are currently in short supply
“Particularly now, when capacity at wafer fabs is tight, it’s important that designers remain agile to access chip manufacturing where it’s available, and where it is cost effective,” said Sowmyan Rajagopalan, the new CEO of Thalia. “The enhancements to Technology Analyzer and Circuit Porting extend our leadership in Analog IP reuse tools enabling automated analysis of the process, options and likely outcomes of moving to new processes or fabs.
The Technology Analyzer helps IP houses and integrated circuit design companies determine if their IP is suitable for cost-effective reuse and also assist with the selection of the optimal process technology for the required application. The software generates a list of electrically comparable devices between the source and target technology i.e. Mapped devices.
The Circuit Porting software facilitates the reuse of existing circuits from the source technology to the target technology, by quickly and efficiently migrating schematics, maintaining the floorplan and electrical values. The software uses electrically comparable mapped devices generated by the Technology Analyzer, during the migration process. This ensures the design after migration to be comparable to the starting design and thereby significantly reduces the iterations during circuit verification.
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