The A-Z steps for building a mixed-signal SOC, Part 6: Layout
Editor’s note: we are continuing our "dialogues" between these two distinguished engineers (Dr. Tamara Schmitz and Dave Ritter) with this special, multipart series on the product development process. This is based on a real-life example and hands-on reality, not speculation or an academic perspective.
This is Chapter Six of the ongoing series; previous entries are:
• Going through a mixed-signal SOC design, from A to Z
• Going through a mixed-signal SOC design, from A to Z, Part 2: defining the concept
• The A-Z steps for building a mixed-signal SOC, Part 3: Packaging and the business plan
• The A-Z steps for building a mixed-signal SOC, Part 4: System design
• The A-Z Steps for building a mixed-signal SOC, Part 5: Circuit simulation
Tamara Schmitz: Hey Dave what are you doing down there?
Dave Ritter: [Sitting on floor of his office trying to sop up a spilled cup of coffee] Hi, Dr. T, just doing some quick cleanup … I’m too embarrassed to call maintenance.
Tamara: [Sits by Dave, and grabs a few paper towels to help] I know what you mean. Pretty basic though: floor work. Reminds me of out next topic.
Dave: How so?
Dr. T: We need to talk about layout, and I believe that starts with floor planning.
Dave: Yes, floor planning. First of all, I’m not much of a layout guy myself. I’ve done a little to help out occasionally, but today’s tools and processes are pretty sophisticated, so there’s always a talented layout person putting the chip together. Actually they are officially called ‘mask designers’, because their output is the data set for making the masks that are used to make the chip.
Dr. T: Does the mask designer know how the chip works? I mean, how would they know how to start, which blocks are critical and which are less so.
Dave: The mask designer knows a great deal about the process and the software, but usually doesn’t know much about a specific chip when he/she starts. So we make a floor plan. Even before that happens, we have hopefully built our schematics hierarchically so that the blocks show clearly in the schematic. Then the floor plan becomes a simple line drawing of where the blocks go. Take a look at Figure 1.
Figure 1: Example of a floorplan.
Dr. T: I get it. You make a simple map of the chip from the schematic. But how do you know – not being a layout person yourself – how big the blocks will be on the chip.
Dave: I guess I make an educated guess. I use the layout tools enough to make a rough guess on sizes, and I base the floor plan on that. We budget area for the blocks. But the mask designer takes a pass at the floor plan and lets me know if things are out of line. It’s interactive between the circuit designer and the mask designer.
Dr. T: So it’s important to keep a good working relationship.
Dave: Yes, and sometimes that’s a challenge. We always try to start layout before all the final simulations are done. In fact, the final sims have to include parasitic derived from the layout, so we can’t do the final sims until layout is nearly done.
Dr. T: How does that affect the mask designer?
Dave: In a word: changes. Mask designers would like us to freeze a design so they can optimize the layout. But late sims may show problems we have to correct. In the end, both mask and circuit designers have to be flexible.
Dr. T: Got it! Once you have a basic floorplan, there must be other inputs the mask designer needs.
Dave: We may know the process, but some things are variable: number of metal layers can change, we may have high values resistors that require another implant and mask step. There may also be a large digital area that is auto routed in software. So each project has a different mix.
Dr. T: I guess that costs go up with number of layers, so why would we use, say, four layers of metal instead of three.
Dave: It depends on the chip. Digital circuits pack much more tightly if we have more interconnect layers, more metal layers. So if the digital area is significant, another layer of metal may make the chip smaller, enough to pay for the added layer.
Dr. T: So the job is to optimize the whole job, not just the number of layers.
Dave: Yes. That’s always the case.
Dr. T: Are there other things like that? You mentioned high value resistors that require another implant. Couldn’t you just use lower values and add many in series to get the resistance you want.
Dave: Yes you can. But if the resistor area grows, it increases parasitic capacitance and can degrade high frequency circuits. And there is always the cost tradeoff: high value resistors will take less area, and in a particular design that may save enough silicon area to pay for the added implant.
Dr. T: Area seems to come up a lot. I guess it’s one of the most basic constraints and cost drivers in a design. So how big are devices, relatively. How does a CMOS transistor compare to a resistor, or a cap?
Dave: I have to give you the typical engineering answer: it depends. Transistors can be very small, and in digital design they usually are. But in analog design a pair of transistors needs to match, and that means they need to be big, or at least big enough. A resistor can be anything from the size of a typical analog transistor to half of the die area. It depends on the design.
But just for the sake of comparison, 1kΩ to 10kΩ resistors are the size of a few typical analog transistors and the size of a few dozen digital transistors… roughly. Capacitors are big. Too big. I build a lot of filters based on RC’s and active amplifiers, and it is not at all unusual for the capacitors to be the biggest thing in the block. Do you recall the 741 op amp?
Dr. T: Of course. The ubiquitous, unity-gain stable 741: I’ve used hundreds of them.
Dave: Well, the largest single device in a 741 op amp is the 30pF compensation capacitor.
Dr. T: Interesting. So you try not to use capacitors.
Dave: No more than necessary.
Dr. T: You mentioned matching. That seems to come up as much as area. What’s the deal?
Dave: A lot of circuit performance depends on the ratio of values, not the absolute values. ADCs, DACs, and bandgaps come to mind. In those blocks we want the key elements to be integer multiples of each other.
We do that by using unit elements: we build resistors, caps and even big transistors as collections of a common small element. That way, we know that R2 is exactly ten times the size of R1 because R2 has 10 unit R1s in series and R1 has only one. See Figure 2.
Figure 2: Scaling resistors by using a unit value.
Dr. T: Wow! And that way we know it is perfect…
Dave: Not quite. Chips can heat unevenly, so all the elements in a resistor may not be at the same temperature, and that will make them mismatch. We get around that geometrically. For example, in a bandgap, we may want one transistor to be 8× another transistor. So we simply place one transistor on the chip, and surround it with 8 other identical devices.
That way, if there is a thermal variation across the block, some the devices will be slightly warmer, some will be slightly cooler, but the average of all 8 surrounding devices will be almost exactly the same as the center device. We call that a common centroid approach. There are lots of tricks of the trade like that.
Dr. T: And it looks like they will have to wait until next time. But at least we cleaned up your coffee. It was a real mess, wasn’t it?
Dave: Yeah. Hey thanks for stopping by… next time maybe we can do my windows!
About the authors
Tamara Schmitz grew up in the Midwest, finding her way west with an acceptance letter to Stanford University. After collecting three EE degrees (BS, MS, and PhD), she taught analog circuits and test-development engineering as an assistant professor at San Jose State University. With eight years of part-time experience in applications engineering, she joined industry full-time at Intersil Corporation as a principal applications engineer
Dave Ritter was at Intersil when he contributed to this series.
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