The analog circuitry hidden at ISSCC

The analog circuitry hidden at ISSCC

Technology News |
By eeNews Europe

Over the next several years, the topics evolved into ways of using transistors to make circuits, such as amplifiers and oscillators (often the former gave rise to the latter). And as time and technology marched on, digital, analog, and mixed-signal circuits evolved, and gave rise to systems-on-a-chip. The keynote talks evolved too, into broad-ranging discussions of technology’s role in society. The conference has come a long way from trying to figure out how transistors work.


The analog technology in this year’s ISSCC is all over the place, and sometimes hidden or well disguised.


For example, take a look at the DRAM and non-volatile memory papers. What could be more digital than a memory chip, right?


I was once told that the two most important guys in a memory company are the process guy who can figure out how to make the storage capacitor or floating gate a little bit smaller, and the analog guy who can design one very good sense amp that can accurately discern a 1 from a 0. The guys who put a billion or so of each on a chip are a lot less important.


One of the papers in the 2013 ISSCC demonstrated how important analog technology is on a Flash memory chip. Paper 12.5 “A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology” authored by a team from Micron Technology, described the challenges in using 20-nm floating-gate cells. It turns out that nearby cells in these tiny geometries interfere with nearby cells. Some of this is solved by careful layout (sounds sort of analog-ish, right?). And to get higher density, multiple bits are stored in each cell, three in this case. That means that the cell needs to be programmed to one of eight voltage levels (using DACs and various charge-pumps), then sensed accurately (using a counter-driven DAC and comparator). All those analog circuits need to be built in this 20-nm process, and have temperature compensation to have any chance of working.


Another paper in the same 2013 session was 12.7 “A 45nm 6b/cell Charge-Trapping Flash Memory Using LDPC-Based ECC and Drift-Immune Soft-Sensing Engine” by engineers from Macronix.


This paper describes the techniques used to store six bits per cell (actually arranged in pairs of three bits/per side of each cell, or so they say). They had to measure the threshold for each level in each cell by trial and error (sort of like a successive-approximation A/D) and apply compensation, as well as an encoding scheme to minimize errors, then a parity check for each cell.


Of course, the outside user only sees 0s and 1s go in and come out. Little does he or she know what’s going on inside. However, without analog technology, these high-density flash memory chips would not exist. And maybe some of those ideas can be used in your analog system design.


Doug Grant is an independent consultant and this article first appeared on EE Times’ Planet Analog website.


Related links and articles:


Terahertz CMOS debuts at ISSCC


4G, Wi-Fi and Ethernet limits pushed at ISSCC


Intel focuses on low power, digital RF


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