The EPAC1.5 – a significant milestone in high-performance computing

The EPAC1.5 – a significant milestone in high-performance computing

Market news |
By Wisse Hettinga

The successful bring-up of EPAC 1.5 is a major step in the development of the EPI common platform

EPAC1.5 is a collection of RISC-V based accelerators designed to push the boundaries of acceleration technologies. This innovative test-chip showcases three distinct approaches to acceleration:

  1. General purpose CPU with dedicated vector unit (VPU)
  2. Many-core stencil/machine learning accelerator (STX)
  3. General Purpose CPU supporting variable precision (VRP)

The EPAC 1.5 design (Figure 1) contains vector processing micro-tiles (VPU) composed of the Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb.

Additional micro-tiles contain distributed Home Nodes (HN) and L2 cache slices (L2), designed respectively by Chalmers and FORTH-ICS, that provide a coherent view of the shared memory subsystem.

The chip also includes the Stencil and Tensor accelerator (STX) designed by ETH Zürich and Fraunhofer IIS and the variable precision processor (VRP) designed by CEA.

All accelerators are interconnected with a very high-speed network on chip with multiple crosspoints (XP) and an off-chip link using SERDES technology from EXTOLL.

The physical design was performed by Fraunhofer IIS using GLOBALFOUNDRIES 22FDX low-power technology. The chip is 27mm2 with 0.3 billion transistors and is hosted on a daughtercard designed by E4 (Figure 2).

The complex bring-up and Linux boot process was carried out at FORTH-ICS, Heraklion, Crete, Greece, and EXTOLL, Mannheim, Germany.

“Seeing a standard Linux distribution’s GUI boot on a chip developed through collaborative efforts within the European Union consortium has been nothing short of thrilling,” declared Filippo Mantovani, the coordinator of the EPAC effort at BSC.

Roger Espasa, founder and CEO of Semidynamics, shared his enthusiasm, stating, “The Avispado core by Semidynamics is an integral part of EPAC, and we take immense pride in our role within this successful EU endeavor. Semidynamics’ development of Avispado has been advanced by EPI funding, propelling the EPAC architecture forward over the past four years.”

Vassilis Papaefstathiou, Head of the bring-up team at FORTH-ICS, added: “It has been an incredible journey for our team from the very early stages of EPAC 1.5 bring-up to booting Linux and running demanding benchmarks. We are extremely proud to be part of the EPI team and contribute to this success.”

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