The keeper of Moore’s Law
IEDM is always eye opening for the advances of device technology. The 2024 meeting in San Francisco this week has not only shown the latest 2nm CMOS process technologies, but way beyond.
TSMC is discussing the technology for its A16 node at the end of 2026, while European researchers at imec have been showing, and making, the components for a standard cell with stacked CFET nanosheet transistors for A7 in the early 2030s.
While there used to be talk of the ‘end of Moore’s Law’ (and certainly the end of Dennard scaling) Intel has been pushing back.
“We continue to be the stewards of Moore’s Law for the industry,” said Sanjay Natarajan, SVP & GM of the Intel Technology Research Group, the newly renamed Components Research group. “We are releasing groundbreaking new technology,” he said. “We have in my opinion perhaps the strongest research development pipeline in the industry.”
He points to the combination of device technology, interconnect and packaging as vital to driving the technology forward.
Imec shows double row CFET standard cell for A7 process node
“We want to stay on the trend we have been on for 50 years and we don’t see a slowing of that trend. The demand is clearly there. If you expand Moore’s Law to a broader view of increasing the performance and scaling through a package, with the transistor and interconnect, we think that trend stays the same.”
“The classic Moore’s Law of transistors on a chip will continue to increase over time, lithography continues to get better with high NA EUV, and we have the first two tools outside of AMSL’s labs in Oregon,” he said.
“Today we are like five year olds with a box of Legos. We don’t have the collective knowledge and all the tools to build the perfect product every time so the challenge for us is how do we get smart fast with advanced packaging technologies and chiplets from all over the global ecosystem,” he added.
“I think we can do that wrong a lot before we fine tune it to get it right by as a whole industry we have to get there fast develop the EDA tools, the correct characterisation of the entire space, there’s a question about reliability. We are in the early stages of figuring things out.”
“Techniques such as directed self-assembly is a pretty exciting option to cram more components on a chip. On top of that you use chiplets and the right 3D packaging.”
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“We have a few papers on transistor technologies,” he said. “We showed a GAA RibbonFET with 6nm gate lengths and a channel thickness of 1.7nm. It paints the roadmap for how we continue to scale GAA with a conventional silicon channel. Now we have made the move to GAA with 18A, we want to continue to scale that for as long as possible in the same way we used FinFET for over a decade, so this is now becoming the era of GAA.”
The next step is to change the channel material to a 2D material, in this case a molybdenum material. “This is a breakthrough technology and the next step for GAA. Then we go a little bit further into the future, describing how you service the long term demand of AI in the trillion transistor era. We really see the need for a huge breakthrough in the reduction of the energy consumption per switch for the technology to scale into the 2030s and 2040s.”
“We are in 1V supply range and we are talking to sub 300mV range, not just one in an academic setting but a trillion of them together so that a decade or 15 years from now this is what everyone is marching towards.”
Interconnect scaling goes hand in hand with transistors and packaging. “We are get getting to region where copper is not acceptable. I think we will continue to use copper where we can but there will be many layers where we need a new solution so we have subtractive Rubidium with a 25% capacitance improvement with the same resistance.”
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With advanced packaging, it has developed techniques for the parallel transfer of 15,000 chiplets in a few minutes. “Selective layer transfer is wafer level die to wafer attach. What we mean is the ability to put two wafers together and select which die to attach with infrared laser de-bonding,” he said. “It really is an industry first that we think will be the mainstay of the industry going forward for chiplets.”
TSMC has been following a similar path with its chiplet assembly technologies such s CoWoS, as well as backside power delivery. This is key for its 16A process that will compete with Intel 14A in 2026.
Called Super Power Rail (SPR) this improves logic density and performance by dedicating front-side routing resource to signals which was shown at IEDM. SPR also improves power delivery and reduces IR drop significantly. Most importantly, the backside contact scheme preserves gate density, layout footprint, and device width flexibility. This achieves the best density and performance simultaneously, and TSMC believes this is a first in the industry.
Like 18A, this is aimed at high performance computing chips and chiplets with complex signal routes and dense power delivery network which benefit the most from backside power delivery. Compared with the 2nm N2P performance process, A16 offers 8%~10% speed improvement at the same Vdd, 15%~20% power reduction at the same speed, and 1.07~1.10X chip density, and TSMC is aiming for production in 2H 2026.
“Intel has a track record of making decisions that the industry recognises and adopts and the backside power via is the latest example of that. What we are proposing for transistors interconnect and package we have put a lot of thought into the longevity so the R&D can be monetised over long enough and does it have any Achilles heel,” said Natarajan at Intel.
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