The Materials scramble from 10nm down to 5nm

The Materials scramble from 10nm down to 5nm

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By eeNews Europe

“For logic [at 14nm, 10nm], the architectures are defined,” notes Raj Jammy, senior VP and GM, Semiconductor Group, at Intermolecular, Inc. “In most cases they are FinFETs, but there is also an alternate option, which is fully-depleted SOI.”

For both 10nm and 7nm, Jammy says that high-k metal gates will tend to be dominant, but the real challenge will be the channel itself. At 10nm, germanium (Ge) will likely be one of the channel materials. “But the moment you add Ge, a whole range of questions open up,” notes Jammy.

Among the questions that he says will need to be answered include:

1.) What kind of gate stacks will be needed with Ge?

2.) What would be the contact scheme on Ge?

3.) How would the industry mix-and-match Ge and silicon channels on the same die?

4.) How would the industry handle the process for the mix/match scheme?

Recognizing the many changes the industry is facing (e.g., HVM EUVL, 450mm wafers, 3D architecture, new packaging technologies, etc.), Jammy considers it vital that the industry come together through partnerships for more competitive R&D, and through consortia for pre-competitive R&D to minimize development costs.

It’s not just process and device development, however. Jammy, who will present at SEMICON West 2014, pointed out that a whole range of new applications coming up from the Internet of Things (IoT) exist that require widely dispersed devices that need to communicate with each other to generate and manage big data while addressing low-power and high-performance requirements.

“What this really means is that for the good of the industry, we must come together and promote cost-effective approaches to developing next-generation technologies. There’s simply no other way to move forward efficiently.” He also makes a case for standardization where possible to ensure that minimal industry resources are focused.

For An Steegen, senior VP, Process Technology at imec, scaling the roadmap is always about finding a balance among the chip power, performance, area, and cost. “As we head to10nm and below, to get the required performance at reduced power, you need to scale Vdd,” said Steegen, who is also presenting at the “Getting to 5nm Devices” session at SEMICON West.

She explained that fully-depleted devices introduced in 20nm/14nm generation devices improve the device electrostatics and therefore enable the Vdd scaling. To further scale devices to the 10nm/7nm generations, Steegen notes that both the device electrostatics and performance will have to be improved. Electrostatics improvement can be accomplished with the introduction of a gate-all-around (GAA) device.

“A technique for performance improvement is to use heterogeneous channel devices such as non-silicon channels,” explained Steegen. “With this scheme, one replaces the silicon in the channel with a higher mobility material, such as Ge, or InGaAs – see figure 1.”

Figure 1: TEM of the first III-V FinFET devices monolithically integrated on 300mm silicon wafers. Source: imec

Imec had some key breakthroughs recently with respect to III-V FinFETs (NFETs). “Ge is very far along too,” noted Steegen. “Pure Ge PFETs are definitely very valuable candidates to go into 10nm or 7nm.” 

Fig. 2: Performance of III-V transistors. Source: imec


How about materials at ~5nm?

It’s a little more difficult to get a clear picture on what will happen between 7nm and 5nm, but Chris Hobbs, Atomic Level Manufacturability program manager at Sematech, believes that the 5nm node is probably the insertion point for III-V channel materials.

While low-temperature processing will be important for transistors at 10nm and 7nm, Hobbs said it becomes especially so when using III-V materials. III-V materials also bring another concern: dealing with the waste water stream that is a result of using arsenic in the process flow; Sematech has a project to address this issue. Developing new in-line metrology processes will be another fab infrastructure issue.

Steegen told SEMI that the consortium has many collaborative efforts in place to deal with new features of metrology tools, as well as new ways of characterizing materials.

“When you start looking into 3D structures and start inserting new materials, to make the flows manufacturable, you need metrology,” said Steegen. Working with suppliers, imec is also be evaluating defect detection in epitaxial materials, as well as overlay and CD metrology for EUV lithography.

Another speaker at SEMICON West 2014, Christopher Borst, associate professor of Nanoengineering at the College of Nanoscale Science and Engineering (SUNY CNSE), told SEMI that, because of the lack of consensus at 10nm and below, there is a multi-pronged effort — often collaborative in nature — to find and develop new channel materials.

“Within the 300mm development line at CNSE, several alternate device architectures are already under development,” said Borst. “Silicon nanowire devices have been developed on 300mm wafers and evaluated for radiation hardened applications.”

Borst noted that this architecture has the potential to provide nearly ideal sub-threshold characteristics and excellent channel control, and can be integrated utilizing the existing 300mm Si tool set. “Difficulties remain with respect to design limitations, gate uniformity and the structural stability of the nanowires through the process flow.”

In parallel with the silicon nanowire effort, CNSE researchers have a development focus on materials beyond Si and are working with industrial and research partner institutions. “III-V layers are being evaluated as channel materials for next-generation devices,” said Borst.

“We are committed to developing modules for III-V gate stack, contact and source-drain engineering that are compliant with environmental guidelines, while driving to sub-10nm device performance targets.” Additionally, the research organization is working on thin-film defectivity improvement in conjunction with integrated process solutions that incorporate a III-V channel.

CNSE is also involved in R&D for the replacement of silicon devices that could incorporate graphene or another 2-D material monolayer. “Graphene is currently the front-running disruptive solution for next-generation device architectures,” Borst told SEMI.

“We are working on the growth, device design, and integrated module development for these layers with a view to their subsequent introduction into mainstream processing.” He noted that the research organization has had success in graphene growth and transfer onto 300mm wafer substrates for clean, repeatable processing.

Scaling wouldn’t be fun without challenges or roadblocks!

On the subject of R&D roadblocks on the scaling path, Jammy links the scaling of logic and memory. “As we move from 14nm to 10nm to 7nm to 5nm, the memory space, particularly driven by NAND, is also progressing quite rapidly,” Jammy told SEMI.

“It is scaling aggressively at this point comparable to logic, and the problems and roadblocks are very common to both.” Jammy counts the move to 3D device architectures as one of the top drivers for both logic and memory, with new materials coming in second – see figure 3 for a summary of key process modules needed for taking III-V materials from lab to fab.

Figure 3: III-V lab to fab. Source: Intermolecular Inc.


Infrastructure and tools are challenges a well, particularly because the industry’s current infrastructure and tools are geared for 2D manufacturing.

“We’ve moved to bit-cost scalable (BiCS) memory, or vertical NAND memory, and at the same time we’ve also started FinFET architectures,” explained Jammy. He notes that the industry hasn’t holistically embraced the question of whether or not current tools are capable of meeting 3D design, fabrication and metrology needs, or just making use of existing tools to transition to 3D.

“For instance, we don’t necessarily have easy solutions for measuring the film thickness on sidewalls of a FinFET structure, or the deep hole of a stacked NAND memory device. If the sixth device in a NAND BiCS memory is somehow different from the rest, we can always error-correct it out, but we don’t know how to prevent it from developing in the first place.”

He further points out that the answers to these questions could lead to completely different approaches to fabrication. “Do we prevent such processing defects, or do we just rely on redundancy and wire it out in an eventual test?”

Jammy maintains that these are the questions the industry will need to ask and answer as it looks toward highly dense 3D device architectures and the need for cost-effective solutions.

For Hobbs, an important scaling challenge to overcome is trying to find a gate stack material that will work on different materials simultaneously. “System-on-a-chip designs use a wide range of devices to build circuits and high-mobility channels might potentially be implemented in only a sub-set of these device types,” said Hobbs.

Finding such a material is attractive in that a standard/common gate stack material could potentially cut down on the number of steps in the process flow, as well as the number of tools in the production line. Still, Hobbs believes that defining the means to commonize the process is premature at this point in time.

With respect to contact materials, Hobbs cited recent work presented by SEMATECH on the use of nickel. “It’s a good contact material that could work for Si, SiGe, Ge, and III-V channel materials,” said Hobbs. “If you think about the new channel materials and the first insertion point, the PMOS and NMOS devices might not have the same channel materials.”

The selection process is a trade-off between integration simplicity and the flexibility to select the best channel material for each device, explained Hobbs. Ge channels are attractive for PMOS and will likely be introduced prior to III-V materials. For NMOS devices, however, III-V channels are attractive. “A single III-V channel material could potentially be used for both NMOS and PMOS with a tradeoff in device performance.”

Aside from ever more complexity, such as more material and architectural options to be investigated and new process steps to develop as the industry proceeds to the next nodes, Steegen sees another issue going forward. “Consolidation, not only at the foundry level, but also at the supplier level, has come to a climax with fewer companies taking up bigger challenges,” Steegen told SEMI.

“Foundries and equipment suppliers need to work together at an earlier stage in process development and need to align their developments even more.”

Steegen believes that stronger and earlier interactions will enable “de-risking” and optimizing development return on investment. “So, there is a need for an R&D platform to enable this closer interaction — a platform that allows involvement of equipment suppliers more deeply in process steps development at an earlier stage than before.”

She envisions imec’s strategic relations with equipment suppliers that develop initial process steps, together with the consortium’s fab partners, as a way to continue scaling.

Other scaling paths

What exactly will happen at 5nm and beyond is not clear, but Jammy has a realistic approach. “If you apply standard economically driven approaches to what scaling might look like at that point, the first thing we recognize is that the purpose of scaling is to add more functionality on a chip,” Jammy told SEMI.

So whether the functionality is achieved through dimensional scaling or some other form of scaling, it’s still scaling. “For a long time, the ITRS and others have proposed that functionality scaling can come from adding more analog, RF and other “More than Moore” components, or by system-in-a-package 3D/2.5D approaches.”

To increase device density and functionality while still driving down power may require the industry to think about how to apply the strengths associated with 3D device architectures to new technologies – see figure 4.

Figure 4: Logic device roadmap. Source: Intermolecular Inc.

“At 5nm, we may have nanowire devices and going beyond that, perhaps we just need to stack these devices in a fashion not very different from what is happening with memory technologies today.”
Following that train of thought, Jammy noted that the industry can start thinking about new methods of device scaling, circuit-level functionality and computing.
“For instance, do we have to build an SRAM cell in a 2D architecture, or can we just build it on a vertical nanowire, figuring out how to wire the different levels?”

He believes that it is the answers to these kinds of questions that will take the industry to 5nm and beyond. “Otherwise, scaling may be a very slow and painful process of diminishing returns.”

Beyond 7nm, when there is essentially no space between the gate and contact, Steegen thinks that there are a couple of different paths for logic. “You can go one way or another into all vertical devices (i.e., vertical nanowires) or stacked devices,” she told SEMI. “When you start stacking devices on top of each other, that is quite a disruptive trend—it’s disruptive for design, and of course, your entire integration and process flow will change.”

High-mobility conductive materials such as graphene, or 2D materials that provide even higher mobility enhancements are being evaluated now for use beyond 7nm. The main question according to Steegen is compatibility with CMOS.

“For bilayer graphene, for example, how would you insert it into a CMOS process flow to make PFETs and NFETs and how would you engineer the band gap,” she pointed out.

For 2D materials (e.g., molybdenum and tungsten-based, diselenide, etc.) the question becomes how would they be integrated?

Borst (SUNY CNSE), Hobbs (Sematech), Jammy (Intermolecular, Inc.), Steegen (imec), — and speakers from Soitec, Sematech, Globalfoundries, and Stanford — will speak at the “Getting to 5nm Devices” session at the new Semiconductor Technology Symposium (STS), to be held July 8-10 as part of the Semicon West 2014 technical and business program agenda.

Learn more about all the front-end sessions and more at Semicon West 2014 –

About the author:

Debra Vogler is a strategy advisor at SEMI, the global industry association serving the nano- and micro-electronic manufacturing supply chains –


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