The move to 3D die stacks drives interconnect consortia
Feature articles |
By eeNews Europe
Cadence® 3D Implementation and Analysis as well as the Wide IO IP solutions are available today. Cadence® 3D DFT and ATPG capabilities are currently in beta release.
Read the full article on page 28 of our January digital edition.
Native RISC-V ROS chip targets robotics
Technology News |
Two European companies are developing a microcontroller chip using the…
By Nick Flaherty
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