The path to 100A at the point of load, and beyond
Introduction
Moore’s Law has brought us immense amounts of computing power through advanced microprocessors and FPGAs. Massive increases in transistor count have made it possible to implement multiple high-speed processors on a single die, each running at speeds up to 3GHz. But these advances in density and performance have increased the number of problems that face engineers working on power delivery for these loads.
To make transistors operate reliably with dimensions an order of magnitude smaller than those employed just a decade ago, processor and FPGA design teams have had to push supply voltages down to 1V or less for the core of the device. Higher voltages would damage the high-speed logic transistors irreparably. As a result, voltages in the 1.8V to 3V range are only used for specialized I/O devices that interface to memory and peripherals.
But the maximum power envelope of server processors and FPGAs is still in the order of tens of watts, and pushing over 100W for the highest-performance products. The result is a current demand that is beginning to exceed the 100A level at the point of load (POL). Using traditional power-conversion architectures, this demand results in the need for larger components able to handle the high stresses involved.
Figure 1: High-performance FPGAs and microprocessors demand high current at a low, tightly controlled voltage.
The traditional approach
The changes could be supported in traditional architectures by devoting more space to the POL converters and decoupling capacitors. But in many of these advanced systems, the available PCB space is not increasing but rather reducing. A further issue is that designing reliable power conversion circuitry able to cope with the high current stresses is a specialized task that is not a core competency for the engineering teams designing PCBs for these advanced processors and logic devices. Without experience in this type of specialized design, the resulting power supply circuitry may be far less than optimal.
The design of low-voltage, high-current POL power delivery is complicated by the problem that conduction-related losses are proportional to the square of the output current (I2out), with DC resistance within the inductors, as well as the power transistors and the wiring structure, being significant contributors. A further issue lies in switching losses. During switching transitions, the control switch has a switching loss proportional to Iout ×Ein and the duration of the switching transition.
The speed of the switching transition is partly governed by the gate turn-off speed of the power transistor, which is limited by a parasitic source inductance that is encountered in standard MOSFET packages. Because of this inductance, the MOSFET can continue to conduct current even though the gate voltage has reached 0V, due the presence of a negative back electromotive force (EMF) caused by the parasitic inductance that pulls the source voltage to a negative level with respect to the gate.
A different approach is needed
Various improvements in device Rds(on), switching characteristics and drive mechanism have pushed the efficiency envelope to a very mature degree such that large improvements through traditional design techniques are difficult to achieve. To deal with low voltages and high currents, a fresh look at the buck converter is needed.
Shifting to a SEPIC-fed buck (SFB) topology, for example, would fundamentally improve power conversion efficiency and transient response, while retaining the simplicity and low cost of the synchronous buck converter. Both conductivity losses (the sum of conduction losses and inductor DCR losses) and switching losses are addressed and to overcome the issue of I2out R losses in the buck converter, multiple energy delivery paths are used to split the load current. This has the result of cutting conduction losses by the square of the current reduction.
Figure 2: Circuit schematic of the SEPIC-fed buck topology, showing the two current paths.
Split current paths
One contribution to the lower losses is a reduction of DC resistance through the inductors for the lower duty cycles that result from the use of a split topology together with the lower output voltages that are required from 100A-capable converters.
The multiple current paths that are fundamental to a SEPIC-fed buck topology reduce the voltage stress on components by almost 50 percent. As a result, the topology can use lower-voltage MOSFETs and capacitors than a standard buck converter design. Because lower-voltage devices tend to exhibit higher conductivity, the topology is able to use MOSFETs with a lower characteristic Rds(on) than equivalent buck-only designs, which further reduces conduction losses. In addition, the combination of a SEPIC and buck section allows input current to be drawn and load current delivered continuously. When the buck section is switched off, the SEPIC converter is active and vice versa.
The efficiency improvements are not just the result of reductions in conduction losses. The SEPIC-buck topology overcomes a number of problems related to the switching losses of standard buck converters, such as the gate turn-off delay. Furthermore, it enables extremely fast turn-off through the use of the topology’s inherent a gate-charge extraction mechanism, which also counteracts the back EMF caused by parasitic source inductance. Due to the lower voltage and current stresses on the power switches, their turn-on losses are significantly reduced as well.
Faster switching and smaller passives
The architecture’s reduced current levels means the integrating inductors and increased reset voltage brings a fundamentally faster response from the power stage. These improvements become even more compelling at higher switching frequencies, which improves overall power density. Tests that we’ve run using this topology (branded by CUI as Solus® Power Topology) show that even using the same switching devices as those employed by a buck design, the SEPIC-fed buck topology has the potential to reduce the switching losses by more than 90 percent. As a result, a converter based on this would operate at a higher switching frequency and reap the benefit of using smaller passive components.
The architecture further benefits designs that provide low-voltage outputs from a higher intermediate voltage. So, as the output-to-input voltage step-down ratio, M, moves from 0.100 to 0.250, the topology’s losses are better than a conventional buck regulator – by 91 percent and 88 percent, respectively. As the ratio increases to 0.660, the efficiency advantage is 70 percent. As a result, the topology is highly suited to POL applications that call for a wide-conversion-ratio.
Figure 3: A comparison of switching losses between a standard buck converter and the SEPIC-fed buck topology of the Solus architecture.
Overshooting
The pressure to deliver energy efficiency from these high-current, low-voltage systems means that the processors and support logic need to move into lower-power modes frequently. But they need to restore full capability extremely quickly without suffering from voltage deviations. For example, a voltage deviation of just two percent can lead to a temporary shutdown that means a web search or VoIP connection fails, costing the service provider potential revenue. Transient response coupled with accurate power delivery is vital in these high reliability systems.
But, having a reduced current in the inductors also brings improvements in transient response. By almost halving the current through its integrated inductors, with respect to the load current in each stage, the load current can rise almost twice as quickly as it could with a standard buck converter. Changes in the applied voltage allow the current to ramp down almost four times faster using a SEPIC-fed buck architecture than a buck when the switch is turned off. Therefore, the power stage is inherently faster under both conditions. The improved transient response reduces the number and size of decoupling capacitors required on the PCB, which translates into further savings in board area.
Adding digital control
This topology handles many of today’s issue in voltage deviations during a transient load step and provides for stable operation, especially under fast-changing conditions. However, by coupling this topology with an advanced digital power controller you are able to create a digitally controlled power sub-system. Through the use of a digital controller circuit it is possible to implement much more advanced compensation and control functions than are possible with traditional analogue circuit-based designs. Another advantage of digital switching regulators is that optimizing the performance of the circuit can be accomplished more easily and automatically.
Historically the compensation function in a digital voltage regulator was manually implemented as proportional, integral and differential (PID) control loops. Initially this was set through a tool that an engineer would utilize to enter all of the external power train components, the tool would then provide the PID entries for the GUI. The behavior of each was controlled by coefficients for each and their combination determined the response of the voltage regulator. This was better than an analog scheme, but still static and geared more towards worst-case conditions.
Dynamic digital PID loop control, where coefficients would be programmed dynamically, made it possible to configure and control the performance of the voltage regulator in real-time under exact conditions. This provided for a more stable performing circuit and allowed the behavior of the system to be monitored and the performance of the voltage regulator circuit to be re-tuned throughout the life of the product. A key advantage of digital implementation is that it allows flexible control architectures, such as allowing multiple loops to operate in parallel.
The SEPIC-fed buck topology needs a digital controller that better aligns with the response capabilities and overall performance enhancements. But, this functionality is being built into some of the latest PWM controllers – see Intersil’s as ChargeMode technology, used in its dual phase digital ZL8800 controller, used by CUI’s latest converters. The zero compensation ZL8800 supports a combination of uniform and multi-rate loop controllers, a technique that makes it possible to provide stable power but react quickly to sudden changes in conditions.
The compensator inside the controller has two parallel paths for processing an error voltage that is sampled at a high rate. One is called the ‘fast path,’ which samples error voltage more frequently than the ‘slow path.’ Using this novel compensator structure, the duty-cycle command is fed back to determine the effect of the fast path and to nullify the fast path effect in the following cycles. This strategy localizes the effect of a voltage change to a few cycles to avoid the instability experienced by less sophisticated PID control strategies that have been optimized for fast response.
The X, Y, and Z axis
Even with changes to the internal architecture that combine to form a highly compact, efficient POL converter, there continues to be space pressures on power supplies. Engineers are, almost universally, under intense pressure to keep PCB area to a minimum and space is rarer than a free plot in Manhattan. But, there may be the scope to go up.
Figure 4: Two versions of modules from CUI within the NDM2Z series
The purpose of a power module is to create a compact form factor that maximizes the advantage of the X, Y, and Z dimensions available. The move towards 100A and higher currents will see engineers get creative and think not just in terms of PCB area, but in PCB volume. And companies changing to meet these needs, for example offering twin form factor POLs, with flat (low profile) and skyscraper (area-saving) variants of each product to fully exploit every available cubic mm. Sometimes the Z axis is unlimited; sometimes it is extremely limited; all possibilities must be addressed with products today.
Summary
Moore’s Law has brought us immense amounts of computing power. But, with the increased sensitivity of today’s processors driving voltages down below 1V for the core of the device, and the power demanded by the highest-performance products being up to 100W and even beyond, the current demand is beginning to exceed 100A.
Space is at a premium so traditional methods, which use larger components to handle the high stresses involved, are not realistic. Instead, to move to 100A and beyond, innovation and abstract thinking on many fronts will be required.
This year’s APEC will be particularly interesting, with the first products to use next generation topologies – such as the SEPIC-fed buck – hitting the market.
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