In the past, when we thought about power optimization, we figured that all we needed to do was shave a bit of power through the use of transistor sizing or process variants. That won’t cut it anymore. Today, power reduction needs to be considered much earlier in the design process – at the register transfer level (RTL) or at the architectural level. Certainly, RTL power reduction is a critical component needed to help meet power budgets, but it is not enough. Chip designers need RTL power estimation and power verification, as well as RTL power reduction to correctly optimize power in their designs.
Read the full article on page 21 of our March digital edition