The year started with the launch of Grai Matter and its edge AI chip, as well as an analysis of the role of IP.
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New chip architectures also emerged, optimised for edge AI. The open source RISC-V instruction set architecture saw various instruction extensions to boost performance for edge AI and so lower the power consumption. While new techniques such as spiking neural networks promised to reduce power consumption further, French AI scientist Yann LeCun at Facebook highlighted the vital role at the RISC-V will play.
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Funders also recognised the growth, backing startups in the middle of the year to get designs to the next stage of development.
- FUNDS FLOOD HARDWARE STARTUPS, SAMBANOVA RAISES $250m
- LOW-POWER CHIP FEATURES QUANTIZED DNN ENGINE
- PERCEIVE LAUNCHES INFERENCE PROCESSOR
- EDGE STARTUP OFFERS LEGACY SUPPORT AND ML ACCELERATION
- FOXCONN, SOCIONEXT AND HAILO PARTNER
- SUMITOMO LEADS $10m BACKING OF ANAGOG
- LOW POWER BREAKTHROUGH FOR INFERENCE CHIPS
By July, details of one of the major chip designs emerged with Blaize having raised $65m. With design teams in the UK, US and India, the company was focussed on both hardware and software.
The edge devices also have to be part of the Internet of Things (IoT)
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Next: Mainstream chips fight back for edge AI
While new chip designs were springing up all over the market, well established technologies were also pushing forwards. Nvidia’s Jetson card was pushing into more embedded applications, while software from Mipsology converted frameworks for inference on FPGAs
Ethics is also emerging as a key factor.
Despite the scepticism earlier in the year, neuromorphic chips also saw plenty of innovation and development.
- DISTRIBUTED AI HELPS ROBOTS RECOGNISE PAIN AND SELF-REPAIR
- ‘AT-MEMORY’ INFERENCE ENGINE RAISES NN PERFORMANCE
- MEMRISTORS COMBINE FERROELECTRICS AND GRAPHENE FOR NEUROMORPHIC CHIPS
- STARTUP RAISES €5m FOR NEUROMORPHIC EDGE CHIP
- GRAI MATTER RAISES $14m FOR SOC ROLL OUT
By December, the RISC-V momentum in edge AI was continuing, with new implementations.
- THREE RISC‑V CORES ADD MULTI-CORE AND SIMD FOR EDGE CHIP DESIGNS
- SWISS SPIN-OFF TO DEVELOP RISC-V CHIP
- ETA COMPUTE PIVOTS WITH SYNAPTICS BACKING
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