Third generation of Renesas’s R-Car SoC targets autonomous driving
The latest R-Car generation brings the right mixture of features to achieve the challenging tasks required to enable cars to drive by themselves: More computing power than ever in this product family, cognitive computing capabilities, high-bandwidth connectivity, a parallel programmable engine offering advanced image recognition technology that offloads the CPU – and all this in compliance with the ISO 26262 functional safety standard.
The first variant of the new R-Car generation bears the name H3, is built around ARM’s 64-bit engine Cortex-A57/A53 and runs at a speed of 40.000 Dhrystone MIPS. For smooth 3D graphics the system has the PowerVR GX6650 graphics engine on board which is based on an architecture from Imagination Technologies and delivers almost three times the shader calculation performance of Renesas’ predecessor model R-Car H2.
The on-chip IMP-X5 parallel programmable engine offers advanced image recognition technology in addition to the CPU and GPU. Exclusive to Renesas, the IMP-X5 recognition engine is optimized for interoperation with the CPU. It delivers four times the recognition performance of the earlier IMP-X4 image recognition engine, embedded in the second-generation R-Car family.
What’s more, the R-Car H3 is the first automotive SoC in the world to adopt the 16nm process. By realizing this high performance as well as compliance with the ISO26262 (ASIL-B) standard for automotive functional safety, the R-Car H3 can be used as an automotive computing platform that supports a wide range of applications, including advanced driving safety support systems and in-vehicle infotainment systems.
To support infotainment applications, in particular rear-seat video infotainment, Renesas has optimised the internal bus architecture of the SoC. As a result, the H3 offers four times the memory bandwidth of the H2, enabling the successor to run multiple applications concurrently. For video infotainment tasks, the system has a proprietary new video codec engine that supports new video compression formats and achieves twice the video playback performance of the H2. The R-Car H3 also incorporates enhanced security functions for a more robust boot protection process as well as protection against external cyber attacks.
SiP modules support high-speed external DDR memory interface design with the R-Car H3. As the connection speed between the SoC and DDR memory rises, and the number of signal lines increases, burdens and complexities of PCB design increase. These have become important issues for system manufacturers. By developing modules with an SoC connected to DDR memory, Renesas is reducing the burden as well as the PCB costs and complexities associated with the design. In addition to the SoC and DDR memory, the modules include serial flash memory required for initial boot-up. This means the design tasks from boot-up through DDR memory operation can be eliminated and system manufacturers adopting the R-Car H3 can reduce their design tasks and risks.
The new R-Car H3 maintains a high level of software compatibility with the other SoCs in the R-Car Family already available. Renesas also assured that the R-Car H3 will maintain high level software scalability for the third-generation R-Car Family.
Samples of the device are available now. Mass production is scheduled to begin in March 2018.
Related news:
Automotive cyber-security: striving for better solutions
Renesas shifts automotive centre of gravity to Europe
The path toward augmented reality with Renesas R-Car family
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
