Three-level flash gives way to four in bid for greater capacity
Flash memory has been a disruptive technology from its industrial inception in the early ’90s and innovation is still ongoing after more than 25 years. Today the most advanced storage products use NAND flash. Thanks to its storage density, quality and reliability NAND has changed our lives. Through continuous development, investments and improvements by flash vendors such as Toshiba and Intel, the technology has become a mainstream consumer product as well as a robust and reliable solution for embedded applications.
The influence of market demand and advancements in manufacturing resulted in 2D NAND reaching its highest point of technological maturity. On the one hand, 2D SLC NAND offers extremely fast access times, low latencies, good energy efficiency and robustness. However, from an economical perspective investing into the production of 2D NAND is not financially viable for vendors anymore, given the demands for larger capacities. Each successive shrink of the cells enabled manufacturers to produce a higher cell count per wafer. Starting out with a cell size of 350nm in 1997 vendors are now able to produce 2D NAND flash cells with a 16nm structure. This in turn led to lower prices for 2D NAND flash and better availability due to a higher GB per wafer yield.
However, the miniaturisation of NAND flash also brought along several technical limitations to flash vendors. One major limitation is that with each shrinking process of the cells the number of available electrons becomes substantially less.
For example, the number of electrons in a flash cell with a lithography of 16nm is around ≤20. A multi-level-cell (MLC) NAND flash has four fixed voltage levels. Each fixed voltage level represents one of the following binary codes: 00, 01, 10, 11. With each successive program and erase cycle the risk of electrons being trapped between the substrate and control gate increases. The more electrons are trapped the higher the chance of voltage levels not being correctly read out by the controller. Without complex controller and firmware features, such as error correction code, the data on the NAND flash would be corrupt and unusable. In the worst case, if the NAND flash contained essential booting data for the operating system, the system put simply, 2D NAND flash has reached its physical limitations. Any further shrinking would undermine the reliability, endurance and data retention of the NAND flash.
From an economical perspective, the market requires storage devices with higher capacities and better performance as our world is becoming more data-centric. Estimations project that an average connected person will interact with smart devices nearly 4800 times per day and that by 2025 163 ZB of data will be created on an annual basis. The unprecedented growth of smart devices in combination with artificial intelligence requires hardware that is capable of handling more storage, processing and analysing of data.
Vendors have taken two major steps to fulfil the markets requirement for larger capacities at an affordable price while at the same time delivering high reliability, uncompromised data integrity and consistent performance.
The first method by vendors to increase storage density was the introduction of a third NAND dimension: multilevel storage. The first NAND flash memories only had a single-level cell (SLC) architecture, and were therefore only capable of storing one bit per memory cell. This was followed by the multi-level cell (MLC) and the triple-level cell (TLC) architectures, which can store two or three bits, respectively. In the MLC, four voltage levels are used to represent the four possible combinations of two binary digits, while the readout circuitry of a TLC has to reliably distinguish between eight discrete voltage levels to capture the three bits of stored data.
and their possible states per memory cell.
The second and more revolutionary method by vendors was to move from the traditional planar NAND structure to a three-dimensional architecture. This architecture is capable of higher areal density in comparison to 2D NAND and provides room for scalability in the future. Just like a skyscraper can shelter more people in comparison to a single storey house, so too can a 3D-NAND flash cell store more data than a 2D flash cell. By having better areal density, vendors can scale to larger capacities by delivering more gigabytes per wafer. This technological leap allows vendors to already produce SSD drives that can go all the way up to 64 TB. Regarding reliability and quality, the BiCs3 NAND flash from Toshiba delivers the same amount of program and erase cycles in comparison to the Toshiba 15nm 2D MLC. However, the price to performance ratio is the key advantage of the technology.
Such three-dimensional NAND (3D NAND) flash memories have therefore taken what was a linear ‘string’ of flash cells making up a word line in a 2D memory array and, conceptually speaking, folded them up into the third dimension in form of a U shape, with each cell being defined by alternating layers of material. The more discrete layers of material that can be laid down by the manufacturing process, the more discrete flash cells can be built in the same die area. Hence the greater the device’s overall capacity.
The future of NAND: 3D QLC with up 512 Layers
NAND Flash technology and the possible stats
per memory cell.
The next logic step is the 3D NAND flash quad level cell (QLC) architecture, which is capable of storing four bits per cell and representing up to 16 different voltage levels. Intel and Micron were the first companies to release a 3D QLC NAND flash product with up to 64-layers. Micron, for example, estimates that using QLC NAND flash instead of legacy hard disk drives would enable datacentres to store 7.7 times more data in the same sized rack. The advanced device architecture of 3D NAND flash will enable vendors to manufacture dies with an even higher number of layers, which in turn further enhances areal density. The fourth-generation devices from Micron and the fifth-generation devices from Samsung, SK Hynix, and Toshiba should allow up to 128 layers. Some companies project that future generations will enable the production of 3D NAND flash with up to 512 layers.
However, the advantages of much greater density do not come without any trade-offs. In terms of performance, in a QLC memory, there are 16 different voltages per cell, which makes writing and reading the data more complex and much slower in comparison to 2D NAND flash. Furthermore, the reliability of the memory decreases relatively rapidly. The validation of individual bits is more demanding and the cells may degrade over several write/erase cycles, making it difficult to determine individual bit values. This may result in data errors. Error correction codes can counter this degradation, but are unable to compensate for the effect entirely. In addition, the program and erase cycles are estimated to be around 500 to 1000, which is significantly lower to 2D and 3D NAND flash architectures.
Ready for big data applications
Given the low number of program and erase cycles, storage products that are fitted with 3D QLC NAND flash are best suited for applications that demand high-speed and frequent read operations, but very few write cycles. Suitable application areas include the real-time analysis of big data, data inputs for artificial intelligence, the provision of media for on-demand services, some database applications, and user authentication. For these applications, the total cost of ownership of QLC NAND based data storage is lower than with HDDs, since users need fewer drives to serve the same volume of data, reducing the power bill while also increasing readout rates. The memory architecture’s density may also make it useful in some embedded and mobile applications.
The first QLC SSD
Intel was the first company to release a 3D QLC (64-Layers) NAND flash product for the mass consumer market: the 660p series. The 660p comes in the space conscious M.2 form factor and offers high capacity drives at an affordable price with PCIe NVMe performance. Due to the higher aerial density of 3D QLC and its ability to store four bits per cell, the 660p can fit up to two times more capacity in an identical M.2 footprint in comparison to an M.2 equipped with 3D TLC NAND flash. The 660p is available with 512GB, 1TB and 2TB. Due to the fast PCIe interface and NVMe protocol, the drive has sequential data rates of up to 1800 MB/s for reading and 1800 MB/s for writing. For both, random read and write, the 660p can perform up to 220k IOPS.
Other suppliers will soon be able to launch QLC based SSDs. Intel, which now develops 3D NAND memory independently of Micron, has announced its first PCIe-based QLC SSD. Toshiba Memory plans to start mass production of its BiCS4 QLC NAND flash in 2019. If you need help understanding how to apply this exciting new technology in your application, Rutronik, as a partner of Apacer, Intel, Swissbit, Toshiba, Transcend, and Wilk, can help. Our storage product managers are in close contact with leading memory vendors and can provide engineers, developers and purchasers with comprehensive support and advice to select the right memory technology.
About the author:
Daniel Zajcev is Product Sales Manager Storage at Rutronik – www.rutronik.com
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