TI aims for the data center with twelve core ARM DSP chips

TI aims for the data center with twelve core ARM DSP chips

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By eeNews Europe

The combination of Cortex-A15 processors and C66x DSP cores, with built-in packet processing and Ethernet switching, is designed to efficiently offload processing in the cloud in enterprise and data center applications as well as high performance computing and video processing.
TI’s six new high-performance SoCs range from dual A15 66AK2E02 up to the quad core, eight DSP 66AK2H12 for applications in the data center from transcoding video formats such as H.265 and JPEG2000 to providing virtual desktops.
TI has used its own on-chip TeraNet interconnect fabric and multicore shared memory controller (MSMC) interface rather than using the ARM cache coherent bus technology, said Tom Flanagan, director of technical strategy for multicore processors at TI. This provides twice the internal bandwidth over the previous generation.
The devices will support OpenCL and OpenMP through a MultiCore Navigator that handles the scheduling of tasks across the multiple cores. The queue of tasks that can be supported has been doubled from 8,000 to 16,000 to handle the increase in cores.
TI is also offering easy-to-use, evaluation modules (EVMs) for less than $1K, reducing developers’ programming burdens and speeding development time with a robust ecosystem of multicore tools and software.
The 66AK2Hx SoCs are currently available for sampling, with broader device availability in 1Q13 and EVM availability in 2Q13. AM5K2Ex and 66AK2Ex samples and EVMs will be available in the second half of 2013. Pricing for these devices will start at $49 for 1 KU.


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