TI and Aricent collaborate on small cell protocol stack optimized for KeyStone multicore processors
This small cell protocol stack is specifically tailored for users of KeyStone-based multicore processors and SoCs. Integrating the field-proven KeyStone architecture elements for layers 2, 3 and transport processing with Aricent’s software components optimizes design efficiencies and enables customers to develop more cost-efficient and high performance base stations.
Rakesh Vij, vice president of business development, Aricent Group comments, "Our small cell protocol stack has been chosen by several leading OEM vendors and is in advanced trials or production systems today. This collaboration further cements our leadership in providing world-class LTE software. Our software together with our product engineering services help OEMs to introduce innovative new solutions to the market quickly and efficiently."
The scalable KeyStone architecture includes support for both TMS320C66x digital signal processors (DSP) generation cores and multiple cache coherent quad ARM Cortex™-A15 clusters, for a mixture of up to 32 DSP and RISC cores. In addition, the KeyStone architecture includes fully offloaded, flexible packet and security coprocessors and capacity expansion for SoC structural elements such as TeraNet, Multicore Navigator and Multicore Shared Memory Controller (MSMC). These structural elements provide a seamless integration between the DSP and ARM RISC cores, allowing base stations developers to fully utilize the capability of all processing elements, including the cores and enhanced AccelerationPacs.