TI claims fastest 16-bit DAC at 2.5 GSPS for 12.5 Gbps JESD204B-compliance

TI claims fastest 16-bit DAC at 2.5 GSPS for 12.5 Gbps JESD204B-compliance

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By eeNews Europe

The DAC38J84 and DAC38J82 provide the bandwidth, performance, small footprint and low power consumption needed for multi-mode 2G/3G/4G cellular base stations to migrate to more advanced technologies, such as LTE-Advanced and carrier aggregation on multiple antennas. The DACs support up to 2 GHz of information bandwidth for wideband power amplifier digital pre-distortion, millimeter wave backhaul infrastructure, signal jamming, radar and test equipment.

An interoperability report is available demonstrating the DAC38J84 with Altera’s Stratix V and Arria V FPGAs. The report provides the guidance designers need to quickly implement a working link between the FPGA and high-speed DAC.

The DACs offer;

Widest frequency bandwidths: The DACs provide an input rate up to 1.23 GSPS per DAC. The DAC38J84 provides two independent transmit paths with up to 1 GHz of complex information bandwidth each – 67% more than the next fastest quad-channel DAC.

Unique multi-band summation: The DAC38J84 is the first quad DAC to integrate a multi-band summation block that allows two complex carrier blocks to be independently mixed to the desired frequency before being summed together for a single path complex transmit. This supports up to 2 GHz of information bandwidth from one pair of 2.5-GSPS output DACs.

Low power: The DAC37J84 consumes 1100 mW at the common wireless base station condition of 1.474 Gsamples/sec, 50% lower than existing 4-channel DACs. At 2.458 Gsamples/sec, the DAC38J84 uses 1612 mW.

Pin-compatible 1.6-Gsamples/sec options: The pin-compatible 4-channel DAC37J84 and 2-channel DAC37J82 run up to 1.6 Gsamples/sec.

Evaluation modules (EVMs) are available to evaluate the performance of the DACs. The DAC38J84EVM, DAC37J84EVM, DAC38J82EVM and DAC37J82EVM include the LMK04828, a JESD204B clock jitter cleaner, which provides the 2.5-GHz DAC clock and multiple SYSREF signals for full JEDEC JESD204B multi-chip synchronisation. An IBIS model is also available to verify board signal integrity requirements.

In the second quarter of 2014, reference designs will be available for all four DACs. The designs will include the LMK04828 JESD204B clock jitter cleaner and two wideband complex modulator options for a complete bits-to-RF solution up to 4 GHz. Modulator options will include the TRF3705 and an upcoming version of the TRF3705 with integrated PLL/VCO.

Samples of all four DACs are available in a 10-mm by 10-mm BGA package. Pricing for 1,000-unit quantities is as follows: $120 for the DAC38J84, $79 for the DAC37J84, $70 for the DAC38J82 and $39.95 for the DAC37J82.


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