Tool base consolidates for 16 nm FinFET design at TSMC
Mentor Graphics announces that its IC design-to-silicon solution has achieved certification for TSMC’s Design Rule Manual (DRM) and SPICE model version 1.0 for its 16nm FinFET process. The certification includes tools in the Calibre physical verification and design-for-manufacturing (DFM) platform, as well as the Olympus-SoC place and route system, the Pyxis custom IC design platform, and Eldo SPICE simulator. Mentor also demonstrated a complete 16nm FinFET digital flow using the Olympus-SoC and Calibre products and the ARM Cortex-A15 MPCore processor as the validation vehicle. The Mentor 16nm solutions are available now to support customers as they transition from test chips to full production 16nm FinFET design efforts.
The Olympus-SoC place and route system enables design closure with support for all 16nm FinFET double patterning (DP), DRC and DFM rules, fin grid alignment for macros and standard cells, and Vt min-area rules support. The new flow also supports low-voltage hold time fixing, interconnect resistance minimisation, signal EM fixing, MiM Cap extraction to address timing impact, and enhanced pin accessibility and routability.
The Calibre nmDRC platform ensures designs meet process requirements. The SmartFill capability in Calibre YieldEnhancer, along with the other Mentor DFM products, Calibre LFD and Calibre CMPAnalyser, were enhanced to meet TSMC-specified requirements for filling, lithography, and CMP simulations for 16FF.
The TSMC 16nm design kit offering for Mentor provides reliability checks based on the Calibre PERC product. This enables customers to analyse and correct issues such as electrostatic discharge (ESD) and latch-up at both IP and full chip level using a common platform and set of checks regardless of the IP source.
To ensure accurate circuit simulation of FinFET devices, Mentor collaborated with TSMC on enhancement and certification of the high-performance Calibre xACT 2.5D and 3D extraction product, and FinFET device models in the Calibre nmLVS product.
The Pyxis custom IC design platform is extended to handle fin grids and provide a fin grid display, and to support guard rings, MOS abutment rules and design rule-driven (DRD) layout. The Eldo simulator has been upgraded to provide accurate FinFET device and circuit level modelling based on the latest BSIM-CMG and TMI models from TSMC.
Mentor Graphics; www.mentor.com
next; Cadence’s announcement on 16nm at TSMC;
Cadence Design Systems has announced its digital, custom and signoff tools have received V1.0 Design Rule Manual (DRM) and SPICE certification for TSMC’s 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence tools. Cadence’s digital, custom/analogue and signoff tools have been co-optimised with TSMC’s 16nm FinFET process to enable higher performance, lower power consumption and smaller area for advanced designs.
The Cadence digital RTL-to-signoff and custom/analogue tools receiving the V1.0 DRM certification are: Cadence Encounter Digital Implementation System, Physical Verification System, QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Analog Design Environment and Spectre Simulator.
Cadence; www.cadence.com
next; Synopsys’ announcement on 16nm at TSMC;
Synopsys has announced availability of the V1.0 certified solution for cell-based and custom implementation with the TSMC N16 FinFET process. The TSMC-certified solution delivers predictable design closure with production-ready FinFET design automation tools. It allows engineers designing the next wave of semiconductors to deliver faster, more power-efficient and denser chips.
Synopsys’ Galaxy Design Platform provides tools and methodology support for customers designing with TSMC’s 16-nm FinFET process:
IC Compiler: Advanced technology supports 16-nm FinFET quantised rules, FinFET grid rules and advanced optimisation methodology, including PBA vs. GBA timing correlation and low-voltage hold time fixing to achieve optimal performance, power and area;
IC Validator: DRC and DPT rule compliance checks verify FinFET parameters, including fin boundary rules and expanding dummy cells;
PrimeTime: Advanced waveform-propagation delay calculation delivers static timing analysis (STA) signoff accuracy required for FinFET processes;
StarRC: Pioneering "real profile" FinFET device modeling provides precise middle-end-of-line (MEOL) parasitic extraction for accurate transistor-level analysis;
HSPICE, CustomSim and FineSim: FinFET device modeling and accurate circuit simulation for the latest FinFET-based designs. In addition, CustomSim delivers new capabilities for electromigration and IR-drop analysis;
Laker: Support for complex FinFET abutment rules, double-patterning, MEOL layers and other advanced-node design requirements.
Synopsys; www.synopsys.com
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