Tool flattens power grids across massive system-on-chip designs

Tool flattens power grids across massive system-on-chip designs

New Products |
By Nick Flaherty

The latest version of the Voltus IC Power Integrity tool now includes an extensively parallel (XP) algorithm option employing distributed processing technology for power grid signoff at advanced 10nm and 7nm process technologies. This new algorithm boosts performance by up to 5X and works on giga-scale designs with near-linear performance scalability on thousands of CPUs and hundreds of machines, and is also cloud ready.

The Voltus-XP technology is aimed at power signoff of very large chip designs at advanced-process technologies in applications such as mobile, high-performance computing (HPC), machine learning, artificial intelligence, networking, automotive, and more. The parallel algorithm also providing much larger capacity than before, any full-chip SoC designs can now be run flat, not only for power-grid IR drop and electromigration (EM) analysis but also electrical and thermal co-analysis at the chip-package-board system level, including 3DIC, with Cadence Sigrity technologies.

The tool has been used at chip designer HiSilicon, with power analysis on complex chips in under a day. 

“We have been using the Cadence Voltus IC Power Integrity Solution to sign off our mobile and HPC production designs because of its high performance and silicon accuracy,” said Zanfeng Chen, design director at HiSilicon. “As the semiconductor industry pushes the envelope on advanced FinFET process nodes, it is crucial that a tool like the Voltus solution stays ahead of the performance curve and allows us to achieve 24-hour turnaround time for power signoff. We are happy to have verified that the extensive parallelism in the Voltus solution can deliver the results in line with our future 5G chip design requirements.”

“The Voltus IC Power Integrity Solution is architected for big design data management with demanding requirements for parallel execution in chip-power calculation, grid parasitic extraction, IR drop and EM analysis,” said Chin-Chi Teng, Cadence vice president and general manager, Digital and Signoff Group. “This unique Voltus-XP technology distributes processing over a large number of machines effectively and provides a high-performance power signoff solution with silicon-proven accuracy, which enables our customers to meet their time-to-market challenges.”

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles