Toolset eases software porting to Tensilica-based multicore SOCs
The Poly-Platform facilitates seamless scalability from single core to multicore architectures, enabling designers to take full advantage of sophisticated compute engines, accelerators and custom configurations. Using a friendly GUI (graphical user interface), the topology can be diagrammed and defined as a map that helps streamline the process of building and running the application. This efficient process significantly cuts development time and lets developers optimize application performance. Several scenarios can be tested in a short period of time.
Chip designers increasingly use multiple Tensilica DPUs in their design, each DPU optimized for a particular function in the data path, such as audio, baseband DSP, security, image processing, or more. Tensilica’s DPUs are easily optimized for these compute-intensive applications.
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