Tortuga tasked by DARPA to bolster chip security
This is designed to address hardware vulnerabilities similar to those exposed by the Spectre and Meltdown threats that have emerged over the last six months.
Tortuga’s design tools are based on its Sentinel language, that can describe hardware security properties at a high level of abstraction. By using Sentinel it is possible to express security requirements at a level that is independent of many implementation details of a design. This allows hardware designers to efficiently specify the security properties they need to verify during the development lifecycle of their hardware design.
Tortuga has been contracted to integrate its current product portfolio of design tools – Prospect and Unison – with emulation platforms. The project will use the Palladium platform from Cadence Design Systems Inc. and the RISC-V processor architecture for initial prototyping and testing.
Tortuga was founded in 2013 as a spin off from University of California in San Diego.
As part of the project, participants in the DARPA program System Security Integrated Through Hardware and Firmware (SSITH) program will receive early access to the resulting security solution for emulation platforms.
SSITH is seeking to close such vulnerabilities as anomalous state detection, meta-data tagging, and churning of the electronic attack surface. The goal of the program is to develop ideas and design tools that will enable system-on-chip (SoC) designers to safeguard hardware against all known classes of hardware vulnerabilities that can be exploited through software, such as exploitation of permissions and privilege in the system architectures, memory errors, information leakage, and code injection.
Tortuga did not mention how much money the contract is worth or over what period of time it will run, but said it’s security solution for emulation platforms will be available for purchase later this year.
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