Toshiba develops circuit techniques for embedded SRAM that consumes 57 percent less power
At the same time, cell failure rate is reduced and fast operation is achieved. Toshiba has demonstrated these techniques in a 40 nm 2 Mb SRAM test chip at 0.5 V. The chip employs three new techniques to achieve stable operation even when the voltage varies or is low.
Embedded SRAM in semiconductor devices for mobile equipment have multiple cells for data storage and must achieve stable performance even if cell characteristics vary. Conventional SRAM techniques employ wordline selection signals for read/write operations. As operating conditions, such as transistor thresholds, temperature and voltage, vary, the optimum wordline voltage at which SRAM cells properly operate also changes.
Toshiba’s new circuit technique predicts SRAM cell failure rate in real time and automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary. The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit technique also eliminates the need to program the wordline level voltage chip by chip, which conventional SRAM require.
When sense amplifier activation timing is adjusted to the slowest cell in low-voltage operation, it becomes too slow in high-voltage operation and SRAM performance slows. The new technique controls wordline voltage so that the voltage characteristics of the control circuit, which determines the sense amplifier activation timing, match the slowest cell’s voltage characteristics. Consequently, activation at the optimum timing is possible at any operating voltage. The technique improves the activation timing in high-voltage operation even if the sense amplifier activation timing is optimized at the lowest operating voltage, resulting in an 18% improvement in operating frequency.
Another issue is an increased malfunction rate for SRAM cells affected by bit lines in read/write operations at low voltage, such as below 0.7 V. Whereas the conventional technique selects wordlines one by one, the new technique simultaneously activates eight wordlines to read/write the same data, achieving operation at voltage as low as 0.5 V, although available memory capacity is reduced.
Toshiba is accelerating development of these techniques and intends to apply them to semiconductor devices capable of operating in a wide voltage range.
1. Circuit for monitoring SRAM memory cell characteristics
Toshiba’s new circuit monitors SRAM cells and achieves stable operation by optimising the wordline voltage when the operating voltage and temperature vary.
2. Technique for optimising the memory read timing in a wide operating voltage range
As the operating voltage increases, activation timing improves. An 18% improvement in operating frequency is achieved at 1.0 V.
3. Technique for operating SRAM cells at low voltage by read/write of the same data in multiple cells
Whereas the conventional technique selects wordlines one by one, the new technique simultaneously activates eight wordlines to read/write the same data, preventing the malfunction at low voltage.
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