Toshiba process technologies target the IoT
A flash memory embedded process based on 65-nm logic process that uses less power than current mainstream technology, and a single-poly non-volatile memory (NVM) process based on 130-nm logic and analogue power process, comprise the two developments. Toshiba says they will enable it to expand its product line-up in such areas as microcontrollers, wireless communication ICs, motor controller drivers and power supply ICs.
The IoT market is seeing strong demand for low power consumption in areas including wearable and healthcare-related equipment. In response, Toshiba has adopted Silicon Storage Technology‘s third-generation SuperFlash cell technology, in combination with its own 65-nm logic process technology. The company has also fine-tuned circuits and manufacturing processes in developing an ultra-low power consumption flash embedded logic process. Microcontrollers for consumer and industrial applications that apply the process can lower power consumption to approximately 60% that of current mainstream technology.
Following the first series of microcontrollers, Toshiba plans to release sample BLE (Bluetooth Low Energy) products, the short-range wireless technology, in fiscal year 2016. The company also plans to apply the 65nm process to its wireless communication IC product family that can optimize use of low power consumption characteristics, including NFC (Near Field Communication) controllers, and contactless cards.
Toshiba suggest that, in addition to low power consumption advantages, the process technology contributes to shorter development time, as application software can be easily written and rewritten to flash memory during development. The company aims to lower power consumption for entire systems, targeting 50 μA/MHz operation, and to develop innovative products for IoT. In applications where significant cost reductions are a concern, Toshiba has developed an NVM embedded process that adopts Yield Microelectronics Corporation‘s single-poly MTP (Multi-time programmable) cells on Toshiba’s 130-nm logic process technology.
NVM and analogue circuits will be embedded on a single chip that can incorporate multiple functions conventionally executed by a multi-chip system. This reduces the number of terminals and realizes smaller packages. Applying MTP specifications for write times improves the new process’s performance while limiting increased steps in mask pattern lithography to three or fewer, [possibly] even, none. By using MTP to adjust output accuracy, Toshiba says it will will expand its product line-up in fields where higher accuracy is essential, such as power management ICs.
Sample shipments of parts in 130-nm NVM and 65-nm flash are scheduled for the 4th quarter of 2015 and the 2nd quarter of 2016, respectively.