Toshiba starts sampling 96-layer, quad bit 3D-NAND

Toshiba starts sampling 96-layer, quad bit 3D-NAND

Technology News |
By Peter Clarke

The memory is a 96-layer device with 4bits per cell (quad level cell or QLC) and is coming to market just over a year after Toshiba had announced each milestone separately (see Toshiba takes 3D-NAND to 96-layers, 4 bits per cell).

The new product achieves the industry’s highest capacity of 1.33Tbit for a single chip, and a 16-die stacked architecture in a single package realizes a capacity of 2.66 terabytes.

“We were among the first in the industry to envision and prepare for the successful migration of SLC technology to MLC, from MLC to TLC, and now from TLC to QLC,” noted Scott Nelson, senior vice president with Toshiba Memory America, in a statement. “This technology evolution has made increasingly dense packaging options available, and QLC will have a game-changing impact across many different markets.”

Samples of Toshiba’s groundbreaking QLC device will begin shipping in early September to SSD and SSD controller vendors for evaluation and development purposes. Mass production is expected to begin in 2019.

Related links and articles:

News articles:

Toshiba takes 3D-NAND to 96-layers, 4 bits per cell

Samsung ramps production of 96-layer 3D-NAND flash

Intel, Micron lag behind Toshiba in 96-layer 3D-NAND, 4bits per cell

Three Chinese firms to launch memory IC production in 2018

SK Hynix takes 3D-NAND to 72 layers

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