Toshiba to sample terabyte memory in April

Toshiba to sample terabyte memory in April

Technology News |
By Peter Clarke

The component will be based on 16 die in a single package with each die being a 512Gbit 64-layer 3D-NAND device with 3-bit-per-cell triple-level cell (TLC).

These 512Gbit non-volatile memories are the latest addition to Toshiba’s BiCS product line, where BiCS stands for bit-cost scalable, and are suitable for applications that need large memory capacities and performance such as enterprise and consumer solid-state drives.

Toshiba works with disk drive company Western Digital on the funding and production of its memory technology and Western Digital announced the 512Gbit 64-layer NAND memory a few weeks ago (see Western Digital doubles 3D-NAND capacity).

Sample shipments of the new 512Gb devices have begun, with mass production scheduled for the second half of 2017.

The use of 64-layer stacking process creates 65 percent advantage in memory capacity per unit area compared with Toshiba’s 48-layer, 256Gbit device, which is in mass production. This increases memory capacity per silicon wafer and leads to a reduction of cost-per-bit.

Toshiba’s has begun construction of Fab 6 and memory-focused R&D center at Yokkaichi in Mie Prefecture, Japan. Fab 6 will be dedicated to the production of BiCS flash.

However Toshiba has also announced that it may sell off all of its chip business to try a plug a multi-billion dollar hole left in its accounts by write-downs on its nuclear power business.

Related links and articles:

News articles:  

Western Digital doubles 3D-NAND capacity

Toshiba starts building next 3D-NAND wafer fab

Toshiba mulls sell off of all of chip business

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