Toshiba’s IP subsystem for 10GbE on SoC; and on Toshiba Structured Array
The IP subsystem consists of a 10 Gigabit Ethernet MAC (media access controller), PCS (physical coding sublayer) and high-speed SerDes (Serialiser Deserialiser) for custom LSI platforms, including ASIC and Toshiba’s FFSA.
FFSA – Fit Fast Stuctured Array is astructured array custom vehicle that incorporates technology from BaySand; it allows complex LSI designs to be quickly implemented (see graphic above) on a pre-diffused silicon substrate by configuring only the interconnect metal layers on the chip. FFSA is a flexible custom LSI solution with pre-designed masters featuring configurable I/Os, SerDes, SRAMs and logic devices that can be configured according to customer requirements.
The 10 G Ethernet IP subsystem implements a 4-lane XAUI or a single Lane XFI interface that provides connectivity to a large number of Ethernet PHYs and controller ASSPs (Application Specific Standard Products). With support for PFC (Priority Flow Control) and a high level of flexibility, the IP subsystem is particularly suited for data centres and telecoms applications.
“Together with Toshiba custom LSI solutions and MoreThanIP proven cores, chip producers will now have an integrated solution at their disposal to help speed the design cycle and meet the needs of the growing high-speed Ethernet market,” said Francois Balay, CEO of MoreThanIP.
Toshiba Electronics Europe; www.toshiba.semicon-storage.com
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