Tower releases 65nm CMOS plus power process

Tower releases 65nm CMOS plus power process

New Products |
By Peter Clarke

The process is intended to provide improvements on the 0.18-micron 5V processes used to address applications in LED lighting, analog switches, DC/DC converters and load switches. It provides an approximate 30 percent area reduction for a given 5V transistor and typically a 35 percent die sized reduction for a mixed-signal chip.

The technology is based on Tower’s automotive 65nm process platform manufactured on 300mm wafers at the former Panasonic wafer fab at Uozu, Japan.

First products have been prototyped for several strategic customers and the technology is now fully released with multilayer masking an multiproject wafer (MPW) runs supported. The first MPW run is expected to run in November 2017.

The advanced 5V 65nm supports high current power applications such as PMIC, DC/DC converters, load switches and point of load ICs using single and dual 3.3um thick copper metal layers.

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