TSMC declares 5nm process ready for design

TSMC declares 5nm process ready for design

Technology News |
By Peter Clarke

The 5nm FinFET process will like the 7nm process before it, initially target advance mobile and high-performance computing applications.

The design infrastructure includes technology files, process design kits (PDKs), tools, design flows between tools and IP cores that have been validated with test silicon production. Companies such as ARM, Cadence and Synopsys collaborated with TSMC to create the design infrastructure.

Compared with TSMC’s 7nm process, the 5nm process delivers 1.8X logic density and a 15 percent speed gain on an ARM Cortex-A72 core. The 5nm process is yielding better than all TSMC’s other processes at same stage in their roll out, TSMC claimed.

“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, vice president of technology development at TSMC, in a statement.

The 5nm PDKs include: device symbols, Pcells, netlisting and files for design, simulation, place and route, dummy fill, and parameter extraction, physical verification and signoff. The Foundation IP includes high-density and high-performance sets of standard cell libraries and memory compilers.

“Several mutual customers have successfully done 5nm production tape-outs using Cadence’s tools, flows and IP for full production development,” said Aniruth Devgan, President, Cadence, in a statement issued by TSMC.

Related links and articles:

News articles:

Intel in the slow lane

5nm tape outs to come 1H19, says TSMC

Update: IMEC, Cadence tape out first 5nm test chip

Cadence gets EDA certification for TSMC’s 5nm and 7nm+ FinFET processes

Samsung to introduce nanosheet transistors in 3nm node

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