TSMC heads below 1nm with 2D transistors at IEDM

Technology News | October 18, 2022

By Nick Flaherty

Materials & processes

Researchers at leading foundry TSMC are developing transistors with feature sizes below 1nm to scale chip designs even further and have shown the first nanosheet transistor with a gate all around (GAA) topology

A strand at the coming IEDM device conference in December is looking at the development of 2D transistors using different materials. The conference, now celebrating 75 years, is an important view of the roadmap for scaling transistor device technology.

The researchers at TSMC have been working with layers of transition metal dichalcogenides (TMDs) such as MoS2 that are just one atom thick. A key challenge of these materials is that it’s quite difficult to deposit pinhole-free dielectric layers, or insulators, onto them. That makes it difficult to incorporate them into the stack of materials which forms a transistor gate.

The team has integrated hafnium-based dielectrics formed by atomic layer deposition with the monolayer TMD material MoS2, to build a top-gated nFET with a physical dielectric thickness of 3.4 nm and an electrically equivalent oxide thickness (EOT) of ~1 nm.

The subthreshold swing (SS) is key in MOSFET transistors, and the devices had a nearly ideal SS of <70 mV/dec.

Another team at TSMC has also developed the first 2D nanosheet transistor with a gate all around (GAA) architecture.

Nanosheet GAA devices are considered the most promising candidate for next-generation device architectures because they offer improved electrostatic control, relatively high drive current and the feasibility of implementing devices with variable widths.

Currently, gate-length scaling and high electrostatic control come from thinning down the Si channel, but in the future extreme gate-length scaling could be enabled by using monolayer TMDs.

While silicon nanosheets integrated with monolayer TMD as the channel material are promising, both the performance of such devices and their potential fabrication processes still need to be explored.

The team built the first-ever monolayer MoS2 nanosheet FET in a GAA configuration. With a gate length of 40nm, the transistor exhibited a current density of ~410 µA/µm at 1V, achieved with a monolayer channel that was ~0.7 nm thick.

The researchers say higher drive current can be achieved by stacking multiple channel layers.

Low-resistance metal contacts to 2D materials are a bottleneck for these transistors.

While progress has been made with n-type contacts for use with nFETs, but low-resistance p-type contacts for use with pFETs are more challenging because of the electro-thermodynamic

A TSMC-led team conducted computational computer modeling and simulation studies to investigate various materials for use as p-type contacts to the 2D material WSe2.

These include metallic contacts using a material like 1T-TiS2, and bulk semimetallic contacts using various materials, of which Co3Sn2S2 was identified as exceptionally good, with a theoretical contact resistance as low as 20 Ω·μm.

Paper #7.4, “Nearly Ideal Subthreshold Swing in Monolayer MoS2 Top-Gate nFETs with Scaled EOT of 1 nm,” T-E Lee and Y-C Su et al, TSMC/National Yang Ming Chiao Tung University/National Applied Research Laboratories.

Paper #34.5, “First Demonstration of GAA Monolayer-MoS2 Nanosheet nFET with 410 μA/μm ID at 1V VD at 40nm Gate Length,” Y-Y. Chung et al, TSMC/National Yang Ming Chiao Tung University/National Applied Research Laboratories Taiwan

Paper #28.1, “Computational Screening and Multiscale Simulation of Barrier-Free Contacts for 2D Semiconductor pFETs,” N. Yang et al, TSMC/Penn State Univ./Univ. Florida/Tohoku Univ./Rice Univ./Texas A&M Univ.

www.ieee-iedm.org

TSMC heads below 1nm with 2D transistors at IEDM

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