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TSMC heads for trillion transistor package with 3nm, 2nm

TSMC heads for trillion transistor package with 3nm, 2nm

Technology News |
By Nick Flaherty



TSMC is developing a complex device for a customer with a trillion transistors, ramping up its competition with Intel as the process technology leader.

It already uses chiplet and substrate technologies for AMD’s MI300 GPU with a 5nm 3D stacked die on a 6nm base substrate with eight DRAM chips. But the technologies are being used for more complex, larger 3nm chips on a substrate.

“We are close to that stage, we have the capability and I can’t announcement a customer’s product,” said Kevin Zhang, senior vice president for business development at the TSMC Technology Symposium in Amsterdam today. “But we have the stacking of multiple large die and the CoWoS process.” Part of the issue is the longer cycle time of 3nm process technology and the added CoWoS process to put all the die together.

“3nm is already a long fab process and then we have to go through the stacking process bit with more product adoption we will see that cycle time come down.  Chiplet technology is still at an early stage.”

The move to the trillion transistor package is driven by the next generation of TSMC’s interposer process, COWoS-L which will be available next year. 

“We are currently developing a 6x reticle size CoWoS-L technology with Super Carrier interposer technology,” said Yujun Li, TSMC’s director of business development for the High Performance Computing Business Division at the symposium. With a reticle size of 858mm(26 mm by 33 mm), this means the system in package will be up to 5148 mm2. This allows more chiplets as well as up to 12 stacks of HBM3 high bandwidth memory. 

The company is planning a 2nm process in 2025, the first with the nanosheet transistor architecture although the main production will be on N2P in 2026 with backside power. “Nanosheet starts at 2nm and it is reasonable to project it will be used for at least a couple of generations easily. For example we used FinFet for five generations, that’s more than ten years.”

The company is also planning to have a 6nm process with resistive RRAM memory available next year for microcontrollers available. “N6 RRAM is further out than 2026,” he said. “MCUs are only just moving to 16nm and usually it takes quite a few years to ramp up in 28nm probably 5 year and then it will move to 6nm.” However MCUs with RRAM are seen as a key capability for zonal architectures in automotive.

www.tsmc.com

 

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