TSMC looks to 2nm process technology
Taiwanese foundry TSMC is working with customers on ways to go to 2nm after its next generation 3nm (N3) process technology.
“We are working with customers on the schedule for the next major node beyond N3,” said CC Wei, chief executive of TSMC. The company has developed a number of technologies that could be used at 2nm. These include nanosheets, 2D and 1D carbon nanotubes.
“For the technology beyond N3 we are optimistic as we are seeing many innovative solutions for scaling,” said YJ Mii, senior vice president of R&D at TSMC. “We have made some major breakthroughs in materials such as 2D and 1D carbon nanotubes, nanosheets and nanowires. This year we have demonstrated a 32bit nanosheet and high mobility materials for 1nm channels. That is a good example of getting technology options ready in advance,” he said.
The current N5 5nm process in volume production today at Fab 18 in Taiwan makes extensive use of 13.5nm extreme UV (EUV) technology that is being used for N3 which will be in volume production in 2022. TSMC is also currently working with UK AI chip designer Graphcore on the larger move to 3nm technology that will be in volume production in the second half of 2021. The current chip, built on 7nm, has 59.4bn transistors. “We have now started to explore what we can achieve using the upcoming 3nm process,” said Dr Maria Marced, president of TSMC Europe.
The N3 process provides a 1.7 increase in logic density over the current N5 process, which would provide over 100bn transistors for Graphcore’s next chip.
However TSMC will currently not commit to a timeline beyond 3nm. “It’s too early for specifics for the next technology platform but we believe we will be able to find a solution on a predictable cadence,” said Kevin Zhuang, SVP of business development. The current cadence would put the N2 2nm process in volume production in 2024.
EUV will be key to 2nm and below, says Mii. “Looking forward we plan to use new masks and materials, new resists and multiple patterning,” he said. “This will enable patterning well beyond N2 (2nm). We are also working with ASML for scanners with a high numerical aperture (NA).”
These technologies will be developed at a new R&D centre. “The first phase started in Q1 and is expected to be completed in 2021 and will house 8000 scientists and engineers,” said Mii.
TSMC has also launched a 4nm process, N4, as a shrink of the current N5 process that is compatible with the current IP and SPICE models but with less masks and higher logic density for a smaller die size to reduce the cost.
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