TSMC looks to standardise chiplet protocols in ‘world changing’ move
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TSMC is looking to develop a standard data format for chiplet designs that would be used by all the EDA design tool and assembly and test providers.
This is part of a move to the 3D Blox technology for building chiplet designs on the TSMC CoWoS process. The aim is to provide common data for chiplets from different silicon suppliers, substrate and PCB makers and the OSAT assembly and test companies.
“Today most of the chips except for the memories come from TSMC but the goal is to mix and match but that is still some way to go but we are trying to get there,” said Dan Kochpatcharin, head of Design Infrastructure at TSMC.
“We have spent the last year working with them to help them understand the collaboration is needed to make 3D IC happen,” he said. “We need substate and PCB makers to talk to each other for a substrate file that can be read by all the EDA vendors – we are working on it and we are 80% there,” he said. “OSAT also does substrate routing so we need to make sure they use the same tools. To integrate all of this is world changing.”
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The latest version of the 3D Blox protocol is already used by Synopsys and Cadence, with Siemens EDA XSI/XPD PCB tools and Ansys supporting it for PCB and substrate analysis and design.
“We made a decision early on that whatever we did would be open so we put the language on line and told EDA partners they could release it to anybody,” he said. “We wanted a single way to modularise this form the connectivity to the wiring and stacking. You need to have early feasibility – when you have 10m bumps how they all line up is important as PCB tools don’t handle millions of bumps.”
Version 2.0 adds stacked dies to the routing tools. “Its not just physical stacking but there is a lot of multi-physics with different thermal, power so different expansions and it not that simple with the through silicon vias and the different choices of interposers,” he said.
The next stage is developing a single format for testing substrates. This is important as the substrate size will grow from the current COWoS-S process technology that is 3.5 times the size of the largest reticle to CoWoS -R and -L that will be up to 6 times the reticle size at 13 x 13cm. “You still need something in between but you will see those coming soon,” he said.
A single format for testing is also necessary he says.
“You need single format for testers an DFT tools so we can make it easier for a tester to do the test, the pin probing locations. The methodology is then on the customer side,” he said.
TSMC is working with ASE and SPIL as part of the Open Innovation Platform (OIP) to further develop the 3D IC technology and is working on projects for automotive chiplets. “We have close to 100 partners in the OIP,” he said. “We don’t just accept anyone – if they join we make sure they support the timeline for the technology so that it is ready for the customer.”
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