TSMC opens up 7nm FINFET process to universities
TSMC has launched a University FinFET Programme to develop future chip design talent for the industry and driving research chips at 7nm.
Educational access for university students, faculty, and academic researchers is centred on the 16nm process design kit (PDK), but TSMC is also offering multi-project wafer (MPW) services at 7nm.
TSMC partners in Europe, Asia and North America will offer universities a range of resources both for teaching and for research projects leading to silicon test chips.
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Design collateral for teaching is based on TSMC’s N16 process, and includes tutorial design cases, training materials and instructional videos, taking students from the conventional planar transistor structure into FinFET designs.
For research projects, TSMC is providing both N16 and N7 process design collateral for test chips to be manufactured via MPW. These include research designs in logic, analog, and radio frequency (RF).
“At TSMC, we are always looking towards the future – not only the future research that will become tomorrow’s technology breakthroughs, but the future talent who will become tomorrow’s innovators,” said Dr. Kevin Zhang, senior vice president of business development at TSMC.
“By offering our 16nm and 7nm technology through the TSMC University FinFET Program, we open a whole new arena for researchers and students to explore their ideas, and fuel their curiosity and passion for the exciting and fast-growing field of semiconductors,” he said.
www.tsmc.com/english/dedicatedFoundry/services/university_program
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