TSMC plans 1.6nm process for 2026
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TSMC is planning a 1.6nm process, called A16, for production in 2026 alongside a wafer-scale chiplet substrate and an automotive chiplet process.
The A16 process uses the TSMC Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals for high performance computing and AI chips with complex signal routes and dense power delivery networks. This will take on Intel’s backside power architecture that is key to the 18A and 14A process nodes.
The A16 TSMC process will provide 8-10% speed improvement at the same supply voltage as the N2P 2nm process, 15-20% power reduction at the same speed, and up to 1.10X chip density improvement.
TSMC’s upcoming N2 technology will come with TSMC NanoFlex with flexibility in 2nm standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Designers are able to optimize the combination of short and tall cells within the same design block, tuning designs to reach the optimal power, performance, and area tradeoffs.
TSMC has also introduced its System-on-Wafer (TSMC-SoW) technology for wafer-scale chiplet substrates. This enables a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.
The first SoW offering, a logic-only wafer based on Integrated Fan-Out (InFO) technology, is already in production and a chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data centre server rack, or even an entire server.
“We are entering an AI-empowered world, where artificial intelligence not only runs in data centres, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”
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TSMC also announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025. N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.
After introducing the N3AE “Auto Early” process in 2023, TSMC is developing InFO-oS and CoWoS-R chiplet processes for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers. These will target AEC-Q100 Grade 2 qualification by fourth quarter of 2025.
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