TSMC plans A14 process for 2028 with Synopsys support
TSMC has shown early details of its next logic process technology, A14.
This is being compared to the 2nm N2 process that is entering production at the moment, rather than the A16 interim process planned for 2026.
A14 is aimed at AI chips in the datacentre but also in smartphones, offering up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. A16 will provide 10% improvement in speed or 20% in power, so there will be less advantage in moving from A16 to A14. This would indicate that TSMC sees its 3nm customers moving to A16 and its 2nm customers moving to A14.
However the power delivery is a key differentiator. A16 has the backside power rail technology it calls SuperPowerRail (SPR) by the end of 2026, while A14 does not, although this is expected to be added to A14A for production in 2029.
Synopsys has certified digital and analog design flows for A16 with backside power routing using its AI-enabled design tools, and is working on the EDA flows on the A14 process.
“Synopsys and TSMC are helping the semiconductor industry speed up the pace of innovation for Angstrom-scale designs by providing mission-critical EDA and IP solutions optimized for the most advanced process technologies,” said Sanjay Bali, Senior Vice President of Strategy and Product Management at Synopsys.
The IC Validator signoff physical verification tool, including Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checking, is certified for A16 and N2P processes. In addition, IC Validator’s high-capacity elastic architecture seamlessly scaled PERC rules to handle TSMC N2P electrostatic discharge (ESD) verification with improved turnaround time.
- TSMC, Synopsys look to A16 backside power routing
- OpenAI joins Apple as customer for TSMC A16 process
TSMC is also improving its NanoFlex nanosheet standard cell architecture with a ‘NanoFlex Pro’ version.
“Our customers constantly look to the future, and TSMC’s technology leadership and manufacturing excellence provides them with a dependable roadmap for their innovations,” said TSMC Chairman and CEO Dr. CC Wei at the company’s technology symposium in San Jose California. “TSMC’s cutting-edge logic technologies like A14 are part of a comprehensive suite of solutions that connect the physical and digital worlds to unleash our customers’ innovation for advancing the AI future.”
TSMC also plans to increase the reticle size of substrates for its Chip on Wafer on Substrate (CoWoS) technology with a 9.5 reticle version in volume production in 2027. This will enable integration of 12 HBM stacks or more in a package together with logic chips such as Nvidia’s Blackwell GPU.
The next generation System-on-Wafer (SoW-X) creates a wafer-sized system with computing power 40X the current CoWoS solution. Volume production is scheduled for 2027.
The Synopsys 3DIC Compiler to support TSMC’s CoWoS technology up to the 5.5x reticle interposer sizes, which has been proven in customer designs for for next-generation HPC and AI chips using wafer-on-wafer and chip-on-wafer advanced packaging. The platform offers high throughput routing automation to enable ultra-high-density interconnects and increased productivity. 3DIC Compiler integrates multi-physics analysis and signoff solutions combined with Ansys simulation technologies for power, thermal, and signal integrity analysis.
The Cadence Integrity 3D-IC Platform now features enhanced support for improved quality of results (QoR) and 3DIC full flow QC with reference flows for 3Dblox, while enabling global resource optimization, chip-package co-design and advanced multiphysics convergence analysis across static timing, power-IR and thermal. New support includes feedthrough creation for multi-chiplet designs and AI-powered tools for end-to-end 3D-IC planning, partitioning and optimization.
Cadence’s Sigrity X technologies and Clarity 3D Solver provide compliance automation for 3Dblox Signal and Power Integrity (SIPI) analysis by integrating with the Cadence Integrity 3D-IC Platform. The integration flow fully automates high-speed S-parameter extraction and transient time domain analysis for the UCIe and HBM channels in these designs.
TSMC is also qualifying its N3A 3nm automotive process to AEC-Q100 Grade-1 with continuous defect improvement to meet Automotive defective parts per million (DPPM) requirements. N3A is entering production for automotive chips for software-defined vehicles.
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