TSMC says 2nm on track for 2025 as it broadens 3nm offer

Technology News | April 28, 2023

By Peter Clarke

TSMC’s next-generation nominal ‘2nm’ manufacturing process is making solid progress and is due to enter production in 2025, the leading foundry said at its North America Technology Symposium. The company also used the symposium to introduce several process additions to the current 3nm generation.

N2 going to the backside

The N2 process is TSMC’s first process to include gate-all-around (GAA) technology, which the foundry calls nanosheets. Samsung has already gone down this route at 3nm while Intel plans to introduce what it calls nanoribbons.

The use of nanosheets provides for a reduction in leakage current by putting the gate all around while the ability to vary the width of the sheets allows for variable drive. N2 will evolve into a family of processes sometime in 2026. N2P will add backside power distribution.

Providing power distribution on the backside of a wafer and then transferring up to active circuitry was an idea first proposed by IMEC research institute several years ago (see IMEC shows backside power delivery with buried power rails).

Separating power and signalling in this way addresses challenges such as elevated via resistances in the back-end-of-line (BEOL). This, in turn, will enhance transistor performance and reduce power consumption. Also, backside power deliver eliminates some potential interference between data and power connections. Ultimately it will allow for higher density ICs at any given node.

N3 generation

The additions to the 3nm node include: N3P providing improved power, performance and density over the original N3 and N3E introductions; N3X tuned for high performance computing (HPC) and N3AE, a process enabling an early start in designing for automotive applications.

The N3 process is in volume production with the enhanced N3E version due to enter production later in 2023

TSMC said the N3P process is due to enter production in 2H24. It will offer an additional boost to N3E with 5 percent more speed at the same leakage current, or 5 to 10 percent power reduction at the same clock frequency. It will also offer a 4 percent increase in chip density.

N3X provides 5 percent more speed compared to N3P at a drive voltage of 1.2V, with the same improved chip density as N3P, and will enter volume production in 2025.

N3AE, or “Auto Early” available in 2023, offers automotive process design kits (PDKs) based on N3E, and allows customers to launch designs on the 3nm node for automotive applications, leading to the fully automotive-qualified N3A process in 2025.

Meanwhile at 4nm TSMC is introducing N4PRF, a process intended to offer CMOS RF for digital intensive applications such as WiFi 7. N4PRF will support 1.77X greater logic density and 45 percent less logic power at the same speed compared with N6RF.

3D packaging

TSMC has in recent years also been a pioneer of 3D packaging and used the Technology Symposium to introduce developments that include:

Chip on Wafer on Substrate (CoWoS) solution with up to 6 times reticle-size for approximately 5,000 square millimetres interposer, capable of accommodating 12 stacks of HBM memory.
SoIC-P, microbump versions of its System on Integrated Chips (SoIC) to provide 3D stacking.
3Dblox1.5, an open standard design language providing automated bump synthesis.