TSMC shows kW integrated voltage regulator for AI
TSMC has shown an Integrated Voltage Regulator (IVR) for AI with five times the vertical power density delivery of a discrete design.
The latest AI datacentre chips are requiring current of 1000A, with the next generation looking to 2000A, or kilowatts of power. One key way to provide such currents is to use vertical power delivery with the power fed into the back of the AI chip.
The IVR developed by TSMC uses a power management IC (PMIC) built on a 16nm process technology that integrates a 2.5nH or 5nH ‘ultra-thin’ inductor with through silicon vias (TSVs).
This PMIC would have ceramic layers to build up the inductor, and the PMIC would sit on a substrate alongside an embedded deep trench capacitor (eDTC) in the interposer layer built using the TSMC CoWoS-L process.
The voltage regulator is built with the eDTCs that provide 1100 to 2500nF for filtering the power, and the TSVs in the regulator provide the link for the printed circuit board to the backside power pads that are available in the 1.6nm A16 process technology.
The combination of the PMIC and capacitors with a kilowatt of power also requires detailed thermal modelling from tools from EDA firms such as Synopsys, Ansys and Cadence Design Systems
However TSMC has not confirmed whether this is a PMIC designed and made by itself, or by a partner. In either case, this is a challenge for implementing the integrated voltage regulator.
TSMC is a pure-play foundry that does not look to compete with its chip design customers and does not recommend specific third party chips, but this is a highly specific, leading edge power chip design. This may well be made available through the TSMC partnership eco-system as an option, and will also stimulate other PMIC designers to produce such chips.
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