TSMC to present 5nm CMOS, 22nm STT-MRAM at IEDM

TSMC to present 5nm CMOS, 22nm STT-MRAM at IEDM

Technology News |
By Peter Clarke

The first is a paper describing the company’s 5nm CMOS technology platform, which is made using extreme ultraviolet (EUV) lithography, and is likely to further establish TSMC as the world’s most advanced chip manufacturer. The 5nm CMOS process is optimized for both mobile and high-performance computing and offers nearly twice the logic density (1.84x) and a 15 percent speed gain or 30 percent power reduction over the company’s 7nm process.

TSMC has engaged with its customers on 5nm and multiple tape outs had been achieved prior to April 2019 (see TSMC declares 5nm process ready for design). The researchers say high-volume production is targeted for 1H20.

With learning from the successful introduction of the 7nm process TSMC has been able to apply EUV lithography to more layers and reduced the total mask count compared with the 7nm process. The transistors include channels engineered for high mobility. The SRAM can be optimized for low power of high performance and the researchers state that the high-density version 0.021 square microns is the highest density SRAM ever reported.

Next: Second paper

The second paper covers TSMC’s addition of spin torque transfer magnetic RAM to a 22nm FinFET process.

STT-MRAM uses magnetic tunnel junctions (MTJs) to store data in magnetic fields rather than as electric charge, but this ability decreases as temperature increases. That makes STT-MRAM both challenging to build – it is fabricated in a chip’s interconnect and must survive high-temperature solder reflow – and also to use in applications such as automotive, where thermal specifications are demanding and the ability to resist outside magnetic fields is critical.

TSMC will describe a versatile 22nm STT-MRAM technology that operates over a temperature range of -40 degrees C to 150 degrees C and retains data through six solder reflow cycles. It demonstrated a 10-year magnetic field immunity of greater than 1100 Oe at 25 degrees C at a 1ppm error rate, and less than 1ppm in a shielded package. The researchers say that by trading off some of the reflow capability and using smaller MTJs, even higher performance can be achieved – such as 6ns read times and 30ns write times, making the process suitable for artificial intelligence inference engines.

Related links and articles:

News articles:

TSMC declares 5nm process ready for design

5nm tape outs to come 1H19, says TSMC

­­­­­EUV lets TSMC shrink chip manufacturing process to 6nm

Report: TSMC to offer embedded ReRAM in 2019

TSMC preps for ‘chiplet’ style manufacturing in 2021

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