TSN IP core turns chips real-time Ethernet ready
Ethernet TSN is advantageous in that it allows data packets with real-time requirements to be prioritized ahead of less time-critical messages, and time-controlled and deterministically transmitted over standard Ethernet hardware throughout widely ramified networks. The TSN IP core includes hardware modules for time synchronization (IEEE 802.1AS) and data stream management (Traffic Shaping) according to IEEE 802.1 Qav and 802.1Qbv standards as well as a dedicated Ethernet MAC for low latency. Available as a synthesizable source code or a netlist, the IP Core uses standard AMBA or Avalon interfaces to facilitate integration with your own circuits and FPGA solutions.
Fraunhofer IPMS – www.ipms.fraunhofer.de
Related articles:
Multiprotocol Gigabit TSN-enabled processors for industry 4.0
Getting started on IEEE’s time-sensitive networking
TSN-MCU integration: who will wait until 2020?
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