TSVs to split more chips: re-integration is the focus

TSVs to split more chips: re-integration is the focus

Technology News |
By eeNews Europe

Barnett Silver, Senior Vice President & Principal at semiconductor consulting firm ATREG gave us his insight on the packaging and IC manufacturing markets.

The total costs for process and fab development has risen dramatically from one node to the next over the last decade, he notes, and only a handful of foundries will have the cash to stay in the race beyond the 14nm node, namely TSMC, Samsung and Intel. That makes OEMs and fabless companies overly reliant on very few foundry options, as rather captive customers. Hence the necessity for large OEMs to vertically re-integrate their strategic silicon supply chain.


Chip integration going full circle: source ATREG.



Silvers sees an inflection point coming over the next three years, when cash-rich OEMs such as Apple, Google or Amazon could invest more and more into foundries and IC packaging facilities to secure their supply chain, have better access to advanced nodes and reduce the risk of silicon allocation. Sitting at the negotiation table of many foundries and IDMs acquisitions/mergers, Silver said he had witnessed such large OEMs making bids (although unsuccessfully so far).

One way to counter TSMC’s unabated foundry market dominance would be for OEMs (Original Equipment Manufacturers) to acquire both OSATS (Outsourced Semiconductor Assembly and Test Services) and foundry shares and develop alternative manufacturing models, with varying levels of capital engagement, operating responsibility and ownership.

Such hybrid semiconductor manufacturing models, as Silver calls them, could include “Equity for Capacity”, where a semiconductor firm or OEM would invest in a fab to have a stake in the overall success of the fab (including guaranteed access to capacity), or more Cooperative (co-op) models, whereby a fab is co-owned and operated among multiple semiconductor firms (ensuring a proportional access to overall capacity while sharing the running expenses).


Advanced packaging will remain a clear differentiator and will drive re-integration: source ATREG.



“In this picture, packaging is essential, yet largely overlooked”, Silver notes, so he sees a convergence of OSATs and foundry services.

Later we learned from Yole Développement that already in 2014, around 19% of overall semiconductor IC wafers were manufactured with packaging features (bumping, RDL, TSV, etc…) processed at the wafer-scale (with still a feature size gap between Silicon device and PCB processing for OSATS to play a role).

“I expect more Mergers & Acquisitions with foundries, OSATs and IDMs all fighting for the USD 51 billion chip assembly & test market. As the packaging gets more advanced, often at wafer-level, there will be re-integration and convergence between the front-end and the back-end”, Silver concluded.

While much progress has been made on TSVs, their resolution, depth, aspect ratio, they are still cost prohibitive for all but high-end applications including server memory or high performance computing. Although 2015 is regarded as the year of the 3D TSV (with several high bandwidth memories ramping up in volume), much of the debate at this year’s European 3D TSV summit was about when such full 3D architectures would compete in consumer applications, cost-wise, with 2.5D interposers. This uncertainty is an opportunity for OSATs to extend their offerings and fight off the foundries’ pretentions to do it all.

According to E. Jan Vardaman, President of semiconductor packaging consulting company TechSearch International Inc., although TSVs are largely used in sensors and MEMS, the yield issues but also the thermal challenges for stacking memory and logic together still make 3D TSV unattractive for consumer applications (something to which would later agree Qualcomm Technologies’ Senior Program Manager, Mustafa Badaroglu).

Vardaman sees monolithic integration of logic and memory happening in 2018 at the earliest, while the price pressure on smartphones would make it difficult to adopt 3D TSVs for logic-on-logic stacking before 2019.

“Die stacking is happening and AMD is doing it”, said Bryan Black, Senior Fellow at AMD as he reviewed today’s 2.5D and 3D packaging solutions, “but why is it happening now?” questioned Black, claiming that AMD had figured out yield issues about ten years ago and is about to use TSVs across all of its product portfolio.

Cost is the first reason, especially when making large dies at advanced nodes becomes cost prohibitive because of decreasing yields. “Silicon integration is running out of gas”, Black says, arguing that the next process node may not necessarily come out cheaper overall.

The uncertainty of transistor costs according to AMD.

His analysis is that even though Moore’s law will give us more transistors at each new node, they will not be the right transistors, because process scaling will stop supporting diverse functionalities on a single die such as fast logic, low power logic, analog, and cache.

Hence, logically, engineers will want to break large single dies into specialized components to maximize the value of new and existing process nodes, only to be re-integrated through 2.5D and 3D stacks. In his view, IC integration will never move away from interposers, but on the contrary, silicon interposers will be the SoCs sockets of the future, hosting multi-sourced 3D components whose functionalities can scale at their own pace.

Silicon interposers will be the SoCs sockets of the future: source AMD.

As the cost of stacked dies will reduce, OEMs will be able to leverage die-sharing instead of soft IP licensing, buying the best dies on the market and assembling them to craft their own SoCs. To do the integration themselves, large OEMs would want to invest in the OSATs or the foundries doing the packaging.

During a coffee break, Black accepted to share more of his thoughts with eeNews Europe.

“In the server space, who knows better than Google or Facebook what they need?” he said. “These guys don’t want to be tied to AMD or Intel’s hardware offerings, but they are not going either to out-innovate semiconductor firms, they just need to add their own innovation”.

“So ideally, they would want an IC with a blank socket in it to do their own things”, commented Black, admitting he had had such discussions with Google engineers.

This die-level IP sharing vision where large OEMs would buy guaranteed tested dies from different vendors and manage their own 2.5D interposer socket, in some cases even adding their own ASIC into the mix, is very much in line with the vertical re-integration scenario envisaged by ATREG.

“It is an interesting time for a business model change”, concluded Black, hinting at the fact that silicon vendors may want to focus on selling more discrete dies of proven IP instead of large do-it-all integrated dies falling short of OEMs’ expectations.

Visit 3D TSV summit organizer SEMI at

Related articles:
Monolithic 3D integration beats next node
Manufacturers’ top tips to cost-effective 3D IC production
3D IC ramp up: what can we learn from MEMS?
FlexTiles European project hints at reconfigurable 3D chips
EUV not needed at 10 or 7nm, says Intel

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