UART IP Core updates long-established standard part features

UART IP Core updates long-established standard part features

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By eeNews Europe

D2692 Dual Universal Asynchronous Receiver/Transmitter is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in one single package. DCD’s IP Core interfaces directly with microprocessors and may be used in a polled or interrupt driven system, as well as providing modem and DMA interface. The operating mode and data format of each channel can be programmed independently. Each receiver and transmitter can select its operating speed as one of 27 fixed Baud rates, a 16x clock derived from a programmable counter/timer, or an external 1x or 16x clock. The opportunity to independently program the operating speed of the receiver and transmitter, makes the UART attractive for dual-speed channel applications such as clustered terminal systems.

Every receiver is equipped with FIFO to minimise the potential of receiver over-run and to reduce interrupt overhead in interrupt-driven systems. The core ensures a flow control capability, to disable a remote DUART transmitter, when the receiver buffer is full. Adding to the function set, there is a multipurpose 7-bit input port and a multipurpose 8-bit output port. They can be used as general purpose I/O ports or can be assigned to specific functions (eg clock inputs or status/interrupt outputs) under program control.

Digital Core Design;

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