UCIe chiplet standard created by industry leaders

UCIe chiplet standard created by industry leaders

Technology News |
By Peter Clarke

A group of ten of the most important technology companies has announced the Universal Chiplet Interconnect Express (UCIe) technology. The proposers claim the existence of UCIe will establish the framework for the development of the chiplet ecosystem.

The move is equivalent to the development of on-chip buses and fabric generators that were used to ease the integration of IP cores from multiple sources for monolithic integration on SoC silicon.

The ten companies are: Advanced Semiconductor Engineering, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and Taiwan Semiconductor Manufacturing Co. These companies are involved in business across a broad range of activities including: semiconductors, packaging, intellectual property supplier, foundry and cloud service provision.

In a statement they said the UCIe 1.0 specification has been ratified to provide a die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing. The goal is to allow end-users to mix and match chiplet components from multiple vendors to bring together customized chiplet-based SoC components.

Now that these ten companies have created what they are describing as an open standard they are encouraging other companies and institutions to join the movement.

The UCIe 1.0 specification leverages established standards including PCI Express (PCIe) and Compute Express Link (CXL). The specification will be available to UCIe members and available to download on the website (

The membership body is yet to formally created but upon incorporation later this year, member companies will begin work on further aspects of the technology, the announcement said. These aspects include standardizing physical, electrical and interconnect form factors for chiplets, as well as security protocols.

 “The age of chiplets has truly arrived, driving the industry to evolve from silicon-centric thinking to system level planning and placing crucial focus on co-design of IC and package,” said Lihong Cao, director of engineering and technical marketing at ASE, in a statement. He added: “We are confident that UCIe will play a pivotal role in enabling ecosystem efficiencies, by lowering development time and cost through open standards for interfaces between various IPs within a multi-vendor ecosystem as well as utilization of advanced package level interconnect.”

Related links and articles:

Download White paper on UCIe

News articles:

3D packaging drives $11.9 billion capex

Samsung improves interposer-based packaging

Intel invests $3.5 billion in chiplet packaging

TSMC preps for ‘chiplet’ style manufacturing in 202

Chiplet-savvy TSMC to build $10 billion assembly and test plant


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