UCIe scales to 64 Gbit/s for 3nm chiplet interconnect
Alphawave Semi has shown the industry’s first 64 Gbit/s Die-to-Die (D2D) IP subsystem for the Universal Chiplet Interconnect Express (UCIe).
The third generation IP, built on a 3nm process in both standard and advanced packaging at TSMC, follows the most recent Gen2 36 Gbit/s and Gen1 24 Gbit/s implementations, also on a TSMC 3nm process.
This level of interconnect bandwidth enables a bandwidth density of over 20 Tbit/s/mm, with low power and latency. The IP is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in High-Performance Computing (HPC), Data Centres, and Artificial Intelligence (AI) applications.
- First 7nm multi-protocol chiplet
- ARM Neoverrse V3 chiplet
- Alphawave IP renames as it looks to 2nm designs
The design complies with the latest UCIe specification and has a scalable architecture with features for advanced testability, including live per-lane health monitoring.
UCIe D2D interconnects facilitate a range of standard and emerging chiplet connectivity scenarios. Common uses encompass linking compute chiplets for a low-latency, coherent connection via UCIe’s streaming capabilities, as well as connecting compute to I/O chiplets using UCIe interfaces with PCIe, CXL, or Ethernet.
Optical retimers can be used to establish dependable, low-latency optical I/O links through optical engines, enhancing off-system connectivity. This supports the development of low-power, high-speed solutions in data centres and AI/ML systems.
For high performance applications, creating a custom HBM base die using the latest UCIe standard is a cutting-edge approach that involves tightly integrating memory dies with compute dies to achieve extremely high bandwidth as well as a low latency between the components. This allows for reuse of die-to-die interfaces that are already occupied on the main die for core-to-core or core-to-I/O connections. This approach greatly optimizes memory transactions in AI applications.
“The UCIe Consortium is delighted to see members achieving critical milestones like tapeouts, which demonstrate the growing adoption of the UCIe Specification,” said Brian Rea, UCIe Consortium Marketing Work Group Chair. “UCIe is a cornerstone of the chiplet industry, providing a robust solution for high-speed, low-latency die-to-die interconnects. By embracing open standards, we’re empowering the industry to accelerate innovation, reduce time-to-market, and deliver groundbreaking technologies.
“Our successful tapeout of the Gen2 UCIe IP at 36 Gbit/s on 3nm technology builds on our pioneering silicon-proven 3nm UCIe IP with CoWoS packaging,” said Mohit Gupta, Senior VP & GM, Custom Silicon & IP, Alphawave Semi.
“This sets the stage for our Gen3 UCIe IP at 64 Gbit/s, which is on target to deliver high performance, 20 Tbit/s/mm throughput functionality to our customers who need the maximization of shoreline density for critical AI bandwidth needs in 2025.”
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
