The research team has reported on simulations of an array of memory cells to make a random access memory (RAM). These simulations predict that the array would match the performance of DRAM but at hundredth the power consumption, without a destructive read and with the added benefit of non-volatility.
As such the memory is the latest candidate for the role of “universal memory” and has been trademarked by the university as UltraRAM.
The non-volatility is due to conduction band offsets of InAs and AlSb, which provides an energy barrier of 2.1eV preventing the escape of electrons. A quantum-mechanical resonant tunnelling mechanism is used to write and erase the memory.
Professor Manus Hayne, who is leading the research, said: “The work published in this new paper represents a significant advance, providing a clear blueprint for the implementation of UltraRAM memory.”
The work was reported in the January 2020 edition of Transactions on Electron Devices. The paper is a follow on to one published in Nature Scientific Reports in June 2019 in which the authors described the use of resonant tunnelling to create a barrier that can be opened and closed with the application of a small voltage.
The paper described both experimental and simulation results for a floating gate memory structure made of InAs/AlSb/GaSb heterostructures, with InAs used as both floating gate and the junctionless channel. Read, write and erase operations were conducted on a number of 10 micron by 10 micron gate dimension cells.
Theoretical evaluations suggest a switching energy at these dimensions of 2 x 10^-12 joules. Shrinking the device would then theoretically yield a switching energy of 10^-17 joules at the 20nm node, which is 100 and 1000 times smaller than for DRAM and Flash, respectively.
The storage time for such memories was reckoned to be at least 10^6 times longer than DRAM.
The work continues at Lancaster University to demonstrate the manufacturability of working memory chips, including fabrication of arrays of devices, development of readout logic, scaling of devices and implementation on silicon.
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