Ultra low latency high-bandwidth 10G bit TCP offload engine SoC
It also extends the TOE’s capability of providing up to 256 and more concurrent TCP sessions, depending upon FPGA size. The latency of about 100 ns was made possible by patent pending advanced dynamic array search architecture. Optional features in the TOE SoC include a variety of CPU interfaces, PCIe Gen-2/3.
This 10G TOE reduces CPU’s involvement in TCP processing by about 95%, presents a very attractive solution to the latency sensitive financial markets and is a critical building block for the current and future high performance networking equipment in converged IP networks.
It is targeted towards Altera GXIII/IV/V FPGA families and can also be targeted to Xilinx and other FPGA families. Further details are available upon request. The TCP offload engine is scalable and can be customized to suit different types of network traffic.
Visit Intilop Corporation at www.intilop.com
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