Implemented in ST’s 65 nm CMOS process, the ST-MIT microprocessor SoC reduces power consumption to10.2 pJ/cycle at 0.54 V, while the SRAM memory cells can operate at 0.4 V. Memory-access power consumption is further reduced through the use of a small latch-based instruction and data caches at the first level of the hierarchy.
Additional features that make this SoC a compact and self-contained system include on-chip ultra low power clock generation and analog-to-digital conversion, as well as a set of peripherals, such as timers and serial interfaces able to work at the minimum voltage supply. “This breakthrough technology can enable the development of an entirely new generation of microprocessors for wireless sensors and implantable medical devices, where minimized power consumption and long battery life are absolutely critical,” said Alessandro Cremonesi, Strategy and System Technology Group Vice President and Advanced System Technology General Manager, STMicroelectronics.
ST is a member of the Microsystems Industrial Group (MIG) at MIT’s Microsystems Technology Laboratories (MTL), an exclusive industry consortium that supports MTL’s infrastructure and provides direction to its research and educational objectives in consultation with the faculty.
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