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UltraSoc moves into big data analytics in system on chip designs

Interviews |
By Nick Flaherty

“The core idea is we put IP into chips that helps get information out that allows you to optimise software for safety and security,” said  Rupert Baines, CEO of Ultrasoc. “The fundamental focus is the embedded silicon IP and that’s where most of our focus has been, but the corollary to that is what do you do with the information. The monitors we have are very smart and configurable so you need a way to get information in to configure them.

“We’ve done a deal with Imperas for their MPD software and libraries so that gives us a truly world class development environment, and we are using TraceAnalyser from Percepio for visualisation. They have a really powerful backend database so you can have gigabytes of data to graph and display that all context sensitive,” he said.

The tools include a library of debug adapters to enable real-time run control of more than 20 processor core architectures from multiple vendors, including Arm, MIPS and RISC-V (as implemented by Andes, Esperanto and SiFive), amongst others

 “We have expanded the RTOS tracing to hardware and software states with all of the semantics and linkages built in and we’ve made it very extensible – there’s an Eclipse framework TCS for plug ins and a link to Python so users can automatically script tests and verification,” he said.

A key addition is hooks for machine learning and data science analytics such as automated anomaly detection, hat mapping and root cause analysis. “This is very much a framework, so talking to our IP in the hardware is exclusively us, but interacting with the outside world is very much plug in and standards based,” said Baines.

Next: Moving into system level monitoring


“It’s a very fluid world in data analytics and we are not claiming we have cracked that but we have some very helpful things we have written, building blocks, but a lot of that will be case by case for a particular customers and we are providing a starting place and they can build on, or if they have something they can plug in.”

“Alibaba have more data scientists than half of Britain so why would be think we would do a better job than them,” he said.

This data analytics capability opens up a whole new discussion with system developers, he says. “For example, for functional safety for validation and safety the analytics can be running live while the chip is running and report safety violations, the same for security, we could be part of a security architecture alerting if an unauthorised process is trying to access protected memory, and we have a very elegant way of optimising software as we are looking at the actual software running so we can see what’s going on in the cache and the memory controller.”

“That’s very different market,” he said. “We are already having discussions with system companies interested n making their product better with better diagnostics.”

UltraDevelop 2 makes use of industry-standard interfaces such as the Eclipse Target Communication Framework (TCF), the GDB Remote Serial Protocol (RSP), Common Trace Format (CTF), and MI, the machine interface layer commonly used to communicate between a debugger’s backend and the IDE front end. It also uses the OpenOCD project and adds custom extensions to provide debug support through its on-chip monitoring and analytics hardware, with the results being released back to the open source community for further development.

UltraDevelop 2 will be available to qualified customers in Q1 2019, with general availability shortly after

www.ultrasoc.com

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