Understanding Flash memory

Understanding Flash memory

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By eeNews Europe

Flash memory overview

Fig. 1: The structure of a Flash storage cell.

The basic storage element used in Flash memory is a modified transistor. In a standard transistor the flow of current through a channel between two contacts is turned on by a voltage applied to a metal  terminal, called the gate, above the channel and separated by an insulating layer of oxide. In a Flash storage cell an extra electrically isolated, or floating, gate is added between the control gate and the channel, as shown in figure 1.


Programming a Flash cell

The Flash cell is programmed by applying a high voltage to the control gate. This causes electrons to pass through the oxide layer to the floating gate (a process known as tunnelling). The presence of these electrons on the floating gate changes the control gate voltage required to turn on the transistor. An erased cell (no charge on the floating gate) will turn on, representing a 1, while a programmed cell will not turn on, representing a 0.

Because the floating gate is surrounded by insulating layers, it will hold the electric charge when the power is removed, making the memory non-volatile.

Erasing a cell reverses this process by applying a large negative voltage to the control gate to force the electrons to tunnel out of the floating gate.

Flash array structure

The Flash memory cells are connected in a hierarchy to allow efficient access, as shown in figure 2. A number of cells, typically 32 to 128, are connected in a string. Strings are organised in blocks. Each string in the block is connected to a separate bitline, and the control gate of each cell in the string is connected to a wordline. A wordline connects to all cells in the same position in the strings, and defines a page within the block. A page is the minimum size for read and programming operations. A block is the smallest unit for erase operations.

Fig. 2: Structure of the cell, page and block.

Multiple blocks can be combined with data buffers and control circuits to form a plane. A complete Flash memory die consists of one or more planes. In devices with multiple planes, it is usually possible to perform read and program operations simultaneously on the planes to increase overall performance.

Data is read by applying a low voltage to the wordline of the page to be read. The data will then appear on the bitlines.

To program cells in a block, the data is put on the bitlines and a high voltage is applied to the wordline of the page to program. Because programming can only change a cell from a 1 to a 0, any cells where the new data is a 1 will be left in their current state, whatever that is. Therefore, all the cells must be erased before writing to ensure that any cells that will not be programmed already contain a 1.

If the cells already contain data then it must be read from the block, combined with the new data and then programmed to a new, erased block. The block where the data was copied from is then ready to be reused after being erased.

Multi-level cells

As described above, each cell stores a single binary value, 0 or 1. It is also possible to inject varying amounts of charge onto the floating gate so that the cell can represent multiple vales. A multi-level cell (MLC) can store four different levels to represent two bits. Similarly, a triple-level cell (TLC) uses eight different levels to store three bits per cell. This allows more data to be stored in an array, reducing the cost per bit. However, the performance is reduced because the programming and read voltages have to be more accurately controlled. For the same reason, MLC Flash memory is more prone to errors.


3D Flash

3D Flash is a new development to further increase density and reduce the cost per bit. This creates the memory structure in three dimensions, rather than just on the surface of the chip. The strings of Flash cells are built vertically in the silicon so that many more bits can be packed into the same surface area. There are a number of technical challenges to creating 3D Flash, but it is already being used to create very large-capacity devices.


Flash controller

The Flash controller provides an interface between the host system and Flash memory devices. It has a number of functions, including mapping the addresses provided by the host to locations in the Flash memory. It also has to manage the inherent shortcomings of the technology.

Error detection and correction

Because of the possibility of errors in the data read from a Flash array, the Flash controller will add extra bits containing an error-correcting code (ECC) when data is written to the Flash. The ECC code is checked when the data is read, which enables single-bit errors to be corrected and multiple-bit errors to be detected.

Inherent weaknesses of Flash technology

One problem with Flash memory is that it has a limited number of write-erase cycles. The high voltages used cause a small amount of damage to the cells, with the result that they become harder to program and erase over time. Damage to the insulating layers around the floating gate also reduces the time that data can be retained. This limits the useful lifetime of the Flash memory to about 100,000 cycles, or fewer for MLC Flash.

The lifetime of the Flash array can be maximised by ensuring that the number of write-erase cycles is the same for all blocks, a process called wear-levelling. This requires the Flash controller to keep track of which blocks have been used, and select the best block to move data to when new data is written.

The voltages used to program and read cells can cause the charge stored on adjacent cells to be slightly changed, eventually resulting in errors when the data is read. This is a temporary effect that will be corrected next time data is written to those cells. The Flash controller can refresh the contents of cells to prevent data loss, either on a regular basis or when it detects too many errors.

As with any memory device, there will be a small number of blocks that do not work properly because of manufacturing tolerances or defects. There will also be blocks that fail over time, which can be detected when ECC errors are not corrected by writing new data. The controller needs to keep track of these bad blocks and change the way data is mapped onto the array to avoid using them.

The controller manages data storage and hides these inherent shortcomings of NAND Flash technology from the host system. This maximises the performance and lifetime of the Flash memory, making it ideal for applications such as mass storage where reliability is essential.


About the author:

Damien Col is Technical Marketing Manager at Hyperstone – He can be reached at

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