Universal Asynchronous Receiver/Transmitter (UART) soft IP core
The CPU itself can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions, like overrun or framing. The DμART also includes a programmable baud rate generator capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock, for driving the internal transmitter logic. Provisions are also included to use this 16 × clock, to drive the receiver logic. The newest UART Core from Digital Core Design has been also equipped with a processor-interrupt system so that interrupts can be programmed according to the user’s requirements, minimizing the computing required to handle the communications link. The DμART core suits applications where the UART and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip.
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