Update: IMEC, Cadence tape out first 5nm test chip

Update: IMEC, Cadence tape out first 5nm test chip

Technology News |
By eeNews Europe

The tape out is aimed at a process that includes both extreme ultraviolet (EUV) lithography as well as 193nm immersion lithography.

There are no active devices in the tape out, which is just back-end-of-line patterning for metal 2 and metal 3 and the cuts, links and via structures between them. The target transistor is a FinFET and the M2 and M3 information is derived from a full processor design, although the front-end-of-line is not included in the tape out.

Place and Route of the M2 layer. Source: IMEC.

IMEC and Cadence are using a mix of self-aligned quadruple patterning and EUV lithography. Metal pitches were scaled from the nominal 32nm pitch to 24nm pitch to push the limit of patterning. The two parties did not declare which processor was used but such designs are often done with a Cortex-A series processor that is well-characterized at previous node.

Next: More detail

The purpose of manufacturing M2 and M3 is to understand the interaction of  patterning, etch, lithography, metallization, power-performance, process window and rule set learning, said Praveen Raghavan, principal engineer at IMEC.

However, during the place and route with Cadence’s Innovus tool, a full processor was taken with the device model, parasitics and timing closure. Both the full processor and SRAM were placed in the design but for now the tape out is only M2-via-M3.

The team at IMEC plans to expose the tape out in at least three ways.

1. SAQP for M2 and M3 with 193i for the cuts and vias using multi exposure.

2. SAQP for M2 and M3 with EUV for the cuts and vias using single exposure.

3. EUV for M2, M3 and vias with no cuts.

Related links and articles:

News articles:

TSMC turns logic FinFET into ReRAM

Imec looks forward to life after FinFET

It’s crunch time (again) for EUV lithography

CEO interview: Cadence is about enablement, collaboration

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