USB 2.0 device controller core for Lattice FPGAs
System Level Solutions has launched a USB2.0 device controller IP block for Lattice FPGAs.
The IP supports LS at 1.5 Mbit/s, FS at 12 Mbit/s and HS at 480 Mbit/s modes with control, Bulk, Interrupt and Isochronous transfers with Suspend, Resume and Remote Wakeup. The block supports up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints) under software control to allow endpoints to be adapted to specific needs. A simple FIFO interface is used to transfer data over endpoints.
The endpoints can be a printer, camera or sensor systems as well as USB mass storage.
The USB 2.0 Device Controller IP core’s functionality is verified in ModelSim simulation software using a test bench written in Verilog HDL and tested with various USB 2.0 PHY Chip
For quick prototype and reduced design cycle, SLS provides IP core along with add-ons such as License for encrypted IP core, Reference design, Demonstration, Software bundle, Technical documents. Of course, SLS helps their customers by providing pre and post sales technical support for generating programming file and other things.
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