Using copper pillars to increase analog IC power dissipation
What’s old is new again: how often have we heard this saying or observed how technology can recreate itself and follow this saying? Copper pillars have been used for many years in flip chip or high-density semiconductors as a way to create higher-density I/O interconnect from the chip to the lead frame or even to the printed circuit board (PCB), in some cases.
The process is fairly simple. Grow a “pillar” of copper on top of the chip with the assistance of photo resist and properly controlled process techniques. Two benefits of using copper pillars are:
1. Better thermal resistance from the die to the lead frame vs traditional bond wires.
2. Lower interconnect resistance from the die to the lead frame vs traditional bond wires
Both of these offer big advantages when used in analog circuits, especially those that need to conduct or control power.
Figure 1 illustrates the difference in using traditional bond wires and copper pillars when connecting Semiconductors die to a lead frame.
Figure 1. Die to lead frame interconnect, bond wires (left) vs copper pillar (right).
Figure 2 shows the implementation of copper pillar on an analog integrated circuit, its resulting bond to the leadframe and the bottom view of a final package.
Figure 2. Implementation of copper pillar on an analog IC.
A traditional wire-bonded lead frame requires additional area for the bond wires to mount from the die to the lead frame. Therefore, what was previously possible only in a 1.6mm × 1.6mm package can now be produced in a 1mm × 1mm package. The wasted area of the bond wire ‘loop’ is not required since the copper pillar is both the electrical/thermal contact and the mechanical structure which mounts the die to the lead frame.
Products such as high-side switches used to enable power to sections of circuitry are an example of how copper pillars can help reduce size and RDS(ON). The RDS(ON) of a high-side MOSFET which is packaged in a power switch using gold (Au) or Aluminium (Al) wire bonds will be approximately 23mΩ. When the same MOSFET is packaged using copper pillars, the part could now have an RDS(ON) of 8mΩ.
This represents a 3× reduction in RDS(ON) and enables a part which could previously handle a DC current of 2A with a 46mV drop to now conduct up to 3.4A with a corresponding 28mV drop. Additionally, the part can now be packaged in a smaller lead frame because bond wires are no longer used. A smaller package with more current-carrying capability is the end result, see Table 1.
Table 1. Gold Bond wire vs. Copper Pillar resistance comparison
An example of a product using copper pillar technology is Micrel’s MIC94084 high-side switch. This device is mounted in a 0.85mm × 0.85mm MLF (QFN) package and has an RDS(ON) of 67mΩ. Other uses of copper pillar technology are emerging in DC-DC regulators, LDOs, and other power products. The technology of copper pillars will help reduce package size, decrease parasitic resistance of bonding and increase thermal performance in all the products where utilized.
(Note: MLF is a registered trademark of Amkor Technology.)
About the authors
Vince Stueve is a field applications engineer and Sean Montgomery is a senior applications engineer, both at Micrel, Inc (Sunnyvale, CA),
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